Through-silicon via
Encyclopedia
In electronic engineering
, a through-silicon via (TSV) is a vertical electrical connection
(via
) passing completely through a silicon wafer or die
. TSVs are a high performance technique to create 3D packages and 3D integrated circuits, compared to alternatives such as package-on-package
, because the density of the vias is substantially higher, and because the length of the connections is shorter.
, Chip Stack MCM
, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space and/or have greater connectivity. An alternate type of 3D package can be found in IBM's Silicon Carrier Packaging Technology, where ICs are not stacked but a carrier substrate containing TSVs is used to connect multiple ICs together in a package. In most 3D packages, the stacked chips are wired together along their edges; this edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some new 3D packages, through-silicon vias replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as TSS (Through-Silicon Stacking or Thru-Silicon Stacking).
Electronic engineering
Electronics engineering, also referred to as electronic engineering, is an engineering discipline where non-linear and active electrical components such as electron tubes, and semiconductor devices, especially transistors, diodes and integrated circuits, are utilized to design electronic...
, a through-silicon via (TSV) is a vertical electrical connection
Electrical connection
An electrical connection between discrete points allows the flow of electrons . A pair of connections is needed for a circuit.Between points with a low voltage difference, direct current can be controlled by a switch...
(via
Via (electronics)
A via is a vertical electrical connection between different layers of conductors in a physical electronic circuit.- In IC :In integrated circuit design, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers. A via on an integrated circuit...
) passing completely through a silicon wafer or die
Die (integrated circuit)
A die in the context of integrated circuits is a small block of semiconducting material, on which a given functional circuit is fabricated.Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon or other semiconductor through processes such as...
. TSVs are a high performance technique to create 3D packages and 3D integrated circuits, compared to alternatives such as package-on-package
Package on package
Package on package is an integrated circuit packaging method to combine vertically discrete logic and memory ball grid array packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them...
, because the density of the vias is substantially higher, and because the length of the connections is shorter.
TSV technology in 3D packages
A 3D package (System in PackageSystem in package
A system-in-a-package or system in package , also known as a Chip Stack MCM, is a number of integrated circuits enclosed in a single package or module. The SiP performs all or most of the functions of an electronic system, and are typically used inside a mobile phone, digital music player, etc...
, Chip Stack MCM
Multi-Chip Module
A multi-chip module is a specialized electronic package where multiple integrated circuits , semiconductor dies or other discrete components are packaged onto a unifying substrate, facilitating their use as a single component...
, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space and/or have greater connectivity. An alternate type of 3D package can be found in IBM's Silicon Carrier Packaging Technology, where ICs are not stacked but a carrier substrate containing TSVs is used to connect multiple ICs together in a package. In most 3D packages, the stacked chips are wired together along their edges; this edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some new 3D packages, through-silicon vias replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as TSS (Through-Silicon Stacking or Thru-Silicon Stacking).