Elmore delay is a simple approximation to the delay through an RC network in an electronic system. It is often used in applications such as logic synthesis

Logic synthesis

In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...

, delay calculation

Delay calculation

Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and...

, static timing analysis

Static timing analysis

Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...

, placement

Placement (EDA)

Placement is an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuitcomponents within the chip’s core area...

 and routing

Routing (EDA)

In electronic design, wire routing, commonly called simply routing, is a step in the design of printed circuit boards and integrated circuits . It builds on a preceding step, called placement, which determines the location of each active element of an IC or component on a PCB...

, since it is simple to compute (especially in tree structured networks, which are the vast majority of signal nets within ICs) and is reasonably accurate. Even where it is not accurate, it is usually faithful, in the sense that reducing the Elmore delay will almost always reduce the true delay, so it is still useful in optimization.

Elmore delay can be thought of in several ways, all mathematically identical.

• For tree structured networks, find the delay through each segment as the R (electrical resistance
  Electrical resistance
  The electrical resistance of an electrical element is the opposition to the passage of an electric current through that element; the inverse quantity is electrical conductance, the ease at which an electric current passes. Electrical resistance shares some conceptual parallels with the mechanical...
  
  ) times the downstream C (electrical capacitance
  Capacitance
  In electromagnetism and electronics, capacitance is the ability of a capacitor to store energy in an electric field. Capacitance is also a measure of the amount of electric potential energy stored for a given electric potential. A common form of energy storage device is a parallel-plate capacitor...
  
  ). Sum the delays from the root to the sink
  Network flow
  In graph theory, a flow network is a directed graph where each edge has a capacity and each edge receives a flow. The amount of flow on an edge cannot exceed the capacity of the edge. Often in Operations Research, a directed graph is called a network, the vertices are called nodes and the edges are...
  
  .
• Assume the output is a simple exponential, and find the exponential that has the same integral as the true response. This is also equivalent to moment matching with one moment, since the first moment is a pure exponential.
• Find a one pole approximation to the true frequency response. This is a first-order Padé approximation
  Padé approximant
  Padé approximant is the "best" approximation of a function by a rational function of given order - under this technique, the approximant's power series agrees with the power series of the function it is approximating....
  
  .

There are many extensions to Elmore delay. It can be extended to upper and lower bounds, to include inductance

Inductance

In electromagnetism and electronics, inductance is the ability of an inductor to store energy in a magnetic field. Inductors generate an opposing voltage proportional to the rate of change in current in a circuit...

 as well as R and C, to be more accurate (higher order approximations) and so on. See delay calculation

Delay calculation

Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and...

for more details and references.