GDDR5
Encyclopedia
GDDR5 SDRAM
is a type of high performance DRAM graphics card memory
designed for computer applications requiring high bandwidth
. Unlike its predecessor, GDDR4
, GDDR5 is based on DDR3 SDRAM
memory which has double the data lines compared to DDR2 SDRAM
, but GDDR5 also has 8-bit wide prefetch buffer
s similar to GDDR4
.
GDDR5 SGRAM conforms to the standards which were set out in the GDDR5 specification by the JEDEC
. It uses an 8n-prefetch
architecture and DDR
interface to achieve high performance operation and can be configured to operate in ×32 mode or ×16 (clamshell) mode which is detected during device initialization. The GDDR5 interface transfers two 32-bit
wide data words per write clock (WCK) cycle to/from the I/O pins. Corresponding to the 8n-prefetch, a single write or read access consists of a 256-bit wide two CK clock cycle data transfer at the internal memory core and eight corresponding 32-bit wide one-half WCK clock cycle data transfers at the I/O pins.
GDDR5 operates with two different clock types. A differential command clock (CK) as a reference for address and command inputs, and a forwarded differential write clock (WCK) as a reference for data reads and writes. Being more precise, the GDDR5 SGRAM uses two write clocks, each of them assigned to two bytes. The WCK runs at twice the CK frequency. Taking a GDDR5 with 5 Gbit/s data rate per pin as an example, the CK clock runs with 1.25 GHz and WCK with 2.5 GHz. The CK and WCK clocks will be aligned during the initialization and training sequence. This alignment allows read and write access with minimum latency.
A single 32-bit GDDR5 chip has about 67 signal pins and the rest are power and grounds in the 170 BGA
package.
Qimonda
, a spin-off of Infineon, has demonstrated and sampled GDDR5, and released a paper about the technologies behind GDDR5. On May 10, 2008, Qimonda announced volume production of 512 Mbit
GDDR5 modules rated at 3.6 Gbit/s (900 MHz), 4.0 Gbit/s (1 GHz), and 4.5 Gbit/s (1.125 GHz).
Hynix Semiconductor introduced the industry's first 1 Gib
GDDR5 memory. It supports a bandwidth of 20 GB/s on a 32-bit bus, which enables memory configurations of 1 GiB
at 160 GB/s with only 8 circuits on a 256-bit bus. Hynix 2 Gbit GDDR5 boasts a 7 GHz clock speed. The newly developed GDDR5 is the fastest and highest density graphics memory available in the market. It operates at 7 GHz effective clock-speed and processes up to 28 GB/s with a 32-bit I/O. 2 Gbit GDDR5 memory chips will enable graphics cards with 2 GiB or more of onboard memory with 224 GB/s or higher peak bandwidth. The memory maker claims that the new chip will be in demand in the second half of 2010.
On June 25, 2008, AMD
became the first company to ship products using GDDR5 memory with its Radeon HD 4870 video card
series, incorporating Qimonda's 512 Mbit memory modules at 3.6 Gbit/s bandwidth.
SDRAM
Synchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...
is a type of high performance DRAM graphics card memory
Random-access memory
Random access memory is a form of computer data storage. Today, it takes the form of integrated circuits that allow stored data to be accessed in any order with a worst case performance of constant time. Strictly speaking, modern types of DRAM are therefore not random access, as data is read in...
designed for computer applications requiring high bandwidth
Bandwidth (computing)
In computer networking and computer science, bandwidth, network bandwidth, data bandwidth, or digital bandwidth is a measure of available or consumed data communication resources expressed in bits/second or multiples of it .Note that in textbooks on wireless communications, modem data transmission,...
. Unlike its predecessor, GDDR4
GDDR4
GDDR4 SDRAM is a type of graphics card memory specified by the JEDEC Semiconductor Memory Standard. It is a rival medium to Rambus's XDR DRAM...
, GDDR5 is based on DDR3 SDRAM
DDR3 SDRAM
In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s...
memory which has double the data lines compared to DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
, but GDDR5 also has 8-bit wide prefetch buffer
Prefetch buffer
A prefetch buffer is a data buffer employed on modern DRAM chips that allows quick and easy access to multiple data words located on a common physical row in the memory....
s similar to GDDR4
GDDR4
GDDR4 SDRAM is a type of graphics card memory specified by the JEDEC Semiconductor Memory Standard. It is a rival medium to Rambus's XDR DRAM...
.
GDDR5 SGRAM conforms to the standards which were set out in the GDDR5 specification by the JEDEC
JEDEC
The JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council , is an independent semiconductor engineering trade organization and standardization body...
. It uses an 8n-prefetch
Prefetch buffer
A prefetch buffer is a data buffer employed on modern DRAM chips that allows quick and easy access to multiple data words located on a common physical row in the memory....
architecture and DDR
Double data rate
In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition....
interface to achieve high performance operation and can be configured to operate in ×32 mode or ×16 (clamshell) mode which is detected during device initialization. The GDDR5 interface transfers two 32-bit
32-bit
The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....
wide data words per write clock (WCK) cycle to/from the I/O pins. Corresponding to the 8n-prefetch, a single write or read access consists of a 256-bit wide two CK clock cycle data transfer at the internal memory core and eight corresponding 32-bit wide one-half WCK clock cycle data transfers at the I/O pins.
GDDR5 operates with two different clock types. A differential command clock (CK) as a reference for address and command inputs, and a forwarded differential write clock (WCK) as a reference for data reads and writes. Being more precise, the GDDR5 SGRAM uses two write clocks, each of them assigned to two bytes. The WCK runs at twice the CK frequency. Taking a GDDR5 with 5 Gbit/s data rate per pin as an example, the CK clock runs with 1.25 GHz and WCK with 2.5 GHz. The CK and WCK clocks will be aligned during the initialization and training sequence. This alignment allows read and write access with minimum latency.
A single 32-bit GDDR5 chip has about 67 signal pins and the rest are power and grounds in the 170 BGA
Ball grid array
A ball grid array is a type of surface-mount packaging used for integrated circuits.- Description :The BGA is descended from the pin grid array , which is a package with one face covered with pins in a grid pattern. These pins conduct electrical signals from the integrated circuit to the printed...
package.
Qimonda
Qimonda
Qimonda AG, was a memory company split out of Infineon Technologies on 1 May 2006, to form at the time the second largest DRAM company worldwide, according to the industry research firm Gartner Dataquest...
, a spin-off of Infineon, has demonstrated and sampled GDDR5, and released a paper about the technologies behind GDDR5. On May 10, 2008, Qimonda announced volume production of 512 Mbit
Megabit
The megabit is a multiple of the unit bit for digital information or computer storage. The prefix mega is defined in the International System of Units as a multiplier of 106 , and therefore...
GDDR5 modules rated at 3.6 Gbit/s (900 MHz), 4.0 Gbit/s (1 GHz), and 4.5 Gbit/s (1.125 GHz).
Hynix Semiconductor introduced the industry's first 1 Gib
Gibibit
The gibibit is a multiple of the bit, a unit of digital information storage, prefixed by the standards-based multiplier gibi , a binary prefix meaning 230. The unit symbol of the gibibit is Gibit or Gib....
GDDR5 memory. It supports a bandwidth of 20 GB/s on a 32-bit bus, which enables memory configurations of 1 GiB
Gibibyte
The gibibyte is a standards-based binary multiple of the byte, a unit of digital information storage. The gibibyte unit symbol is GiB....
at 160 GB/s with only 8 circuits on a 256-bit bus. Hynix 2 Gbit GDDR5 boasts a 7 GHz clock speed. The newly developed GDDR5 is the fastest and highest density graphics memory available in the market. It operates at 7 GHz effective clock-speed and processes up to 28 GB/s with a 32-bit I/O. 2 Gbit GDDR5 memory chips will enable graphics cards with 2 GiB or more of onboard memory with 224 GB/s or higher peak bandwidth. The memory maker claims that the new chip will be in demand in the second half of 2010.
On June 25, 2008, AMD
Advanced Micro Devices
Advanced Micro Devices, Inc. or AMD is an American multinational semiconductor company based in Sunnyvale, California, that develops computer processors and related technologies for commercial and consumer markets...
became the first company to ship products using GDDR5 memory with its Radeon HD 4870 video card
Video card
A video card, Graphics Card, or Graphics adapter is an expansion card which generates output images to a display. Most video cards offer various functions such as accelerated rendering of 3D scenes and 2D graphics, MPEG-2/MPEG-4 decoding, TV output, or the ability to connect multiple monitors...
series, incorporating Qimonda's 512 Mbit memory modules at 3.6 Gbit/s bandwidth.