OpenRISC
Encyclopedia
OpenRISC is the original flagship project of the OpenCores
community. This project aims to develop a series of general purpose open source
RISC CPU
architectures. The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support.
A team from OpenCores provided the first implementation, the OpenRISC 1200
, written in the Verilog
hardware description language
. The hardware design was released under the GNU Lesser General Public License
(LGPL), while the models and firmware were released under the GNU General Public License
(GPL). A reference SoC implementation based on the OpenRISC 1200 was developed, known as ORPSoC (the OpenRISC Reference Platform System-on-Chip). A number of groups demonstrated ORPSoC and other OR1200 based designs running on FPGA.
As of October 2011, there are still some minor details in the 64-bit specification that are incomplete or ambiguous.
Another notable feature is a rich set of SIMD
instructions intended for digital signal processing.
s which give the possibility to iterate on the design at the cost of performance. As the OpenRISC 1000 is now considered stable the OpenCores project is trying to build a cost-efficient ASIC
with this design to get improved performance. They launched a call for donations in 2011 with the aim to produce the first ASIC in Q1 2012.
. Samsung use the OpenRISC 1000 in their DTV System-on-Chips (SDP83 B Series, SDP92 C-Series, SDP1001 and SDP1002 Series) .
More recently Cadence Design Systems
have started using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed to Accellera
).
to OpenRISC to support development in C
and C++
. Using this tool chain the newlib
and uClibc
libraries have been ported to the processor. Dynalith provides OpenIDEA, a graphical development environment based on this tool chain.
The OR1K project provides an instruction set simulator
, or1ksim. The flagship implementation, the OR1200, is an RTL model in Verilog HDL, from which a SystemC
-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative set up by Imperas.
was gained in version 3.1. The implementation merged in this release is the 32-bit OpenRISC 1000 family (or1k).. Previously µClinux had been ported to the OpenRISC 1000 architecture, but this has now been superseded by the mainline port.
, FreeRTOS
and eCos
.
OpenCores
OpenCores is the world's largest open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies...
community. This project aims to develop a series of general purpose open source
Open source hardware
Open source hardware consists of physical artifacts of technology designed and offered in the same manner as free and open source software . Open source hardware is part of the open source culture movement and applies a like concept to a variety of components. The term usually means that...
RISC CPU
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
architectures. The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support.
A team from OpenCores provided the first implementation, the OpenRISC 1200
OpenRISC 1200
The OpenRISC 1200 is a synthesizable CPU core maintained by developers at OpenCores.org. The OR1200 design is an open source implementation of the OpenRISC 1000 RISC architecture . The Verilog RTL description is released under the GNU Lesser General Public License .-Architecture :The IP core of...
, written in the Verilog
Verilog
In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
hardware description language
Hardware description language
In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic...
. The hardware design was released under the GNU Lesser General Public License
GNU Lesser General Public License
The GNU Lesser General Public License or LGPL is a free software license published by the Free Software Foundation . It was designed as a compromise between the strong-copyleft GNU General Public License or GPL and permissive licenses such as the BSD licenses and the MIT License...
(LGPL), while the models and firmware were released under the GNU General Public License
GNU General Public License
The GNU General Public License is the most widely used free software license, originally written by Richard Stallman for the GNU Project....
(GPL). A reference SoC implementation based on the OpenRISC 1200 was developed, known as ORPSoC (the OpenRISC Reference Platform System-on-Chip). A number of groups demonstrated ORPSoC and other OR1200 based designs running on FPGA.
Instruction set
The instruction set is a reasonably simple example of a modern RISC using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32 and 64 bit versions of the specification, the main difference being the register width (32 or 64 bits) and pagetable layout. The OpenRISC specification includes all features common to modern desktop/server processors: a supervisor mode and virtual memory system, optional read, write and execute control for memory pages, and instructions for synchronization and interrupt handling between multiple processors.As of October 2011, there are still some minor details in the 64-bit specification that are incomplete or ambiguous.
Another notable feature is a rich set of SIMD
SIMD
Single instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously...
instructions intended for digital signal processing.
Implementations
Most implementations are on FPGAField-programmable gate array
A field-programmable gate array is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable"...
s which give the possibility to iterate on the design at the cost of performance. As the OpenRISC 1000 is now considered stable the OpenCores project is trying to build a cost-efficient ASIC
Application-specific integrated circuit
An application-specific integrated circuit is an integrated circuit customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC...
with this design to get improved performance. They launched a call for donations in 2011 with the aim to produce the first ASIC in Q1 2012.
Commercial implementations
Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC (who also maintain the opencores.org website) and the BA12, BA14 and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE FPGA prototyping board, which is capable of running both the OpenRISC 1000 and BA12. Flextronics International and Jennic Limited manufactured the OpenRISC as part of an ASICApplication-specific integrated circuit
An application-specific integrated circuit is an integrated circuit customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC...
. Samsung use the OpenRISC 1000 in their DTV System-on-Chips (SDP83 B Series, SDP92 C-Series, SDP1001 and SDP1002 Series) .
More recently Cadence Design Systems
Cadence Design Systems
Cadence Design Systems, Inc is an electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc...
have started using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed to Accellera
Accellera
Accellera is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation and IC design and manufacturing. It is less constrained than the IEEE and is therefore the starting place for many standards. Once...
).
Toolchain support
The OpenCores community have ported the GNU toolchainGNU toolchain
The GNU toolchain is a blanket term for a collection of programming tools produced by the GNU Project. These tools form a toolchain used for developing applications and operating systems....
to OpenRISC to support development in C
C (programming language)
C is a general-purpose computer programming language developed between 1969 and 1973 by Dennis Ritchie at the Bell Telephone Laboratories for use with the Unix operating system....
and C++
C++
C++ is a statically typed, free-form, multi-paradigm, compiled, general-purpose programming language. It is regarded as an intermediate-level language, as it comprises a combination of both high-level and low-level language features. It was developed by Bjarne Stroustrup starting in 1979 at Bell...
. Using this tool chain the newlib
Newlib
Newlib is a C standard library implementation intended for use on embedded systems. It is a conglomeration of several library parts, all under free software licenses that make them easily usable on embedded products....
and uClibc
UClibc
In computing, uClibc is a small C standard library intended for embedded Linux systems. uClibc was created to support uClinux, a version of Linux not requiring a memory management unit and thus suited for microcontrollers .The project lead is Erik Andersen. The other main contributor is Manuel...
libraries have been ported to the processor. Dynalith provides OpenIDEA, a graphical development environment based on this tool chain.
The OR1K project provides an instruction set simulator
Instruction Set Simulator
An instruction set simulator is a simulation model, usually coded in a high-level programming language, which mimics the behavior of a mainframe or microprocessor by "reading" instructions and maintaining internal variables which represent the processor's registers.Instruction simulation is a...
, or1ksim. The flagship implementation, the OR1200, is an RTL model in Verilog HDL, from which a SystemC
SystemC
SystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...
-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative set up by Imperas.
Linux support
Support for the mainline Linux kernelLinux kernel
The Linux kernel is an operating system kernel used by the Linux family of Unix-like operating systems. It is one of the most prominent examples of free and open source software....
was gained in version 3.1. The implementation merged in this release is the 32-bit OpenRISC 1000 family (or1k).. Previously µClinux had been ported to the OpenRISC 1000 architecture, but this has now been superseded by the mainline port.
RTOS support
A number of real time operating systems have been ported to OpenRISC, including RTEMSRTEMS
RTEMS is a free open source real-time operating system designed for embedded systems....
, FreeRTOS
FreeRTOS
FreeRTOS is a real-time operating system for embedded devices, being ported to several microcontrollers. It is distributed under the GPL with an optional exception...
and eCos
ECos
eCos is an open source, royalty-free, real-time operating system intended for embedded systems and applications which need only one process with multiple threads. It is designed to be customizable to precise application requirements of run-time performance and hardware needs...
.
See also
- OpenCoresOpenCoresOpenCores is the world's largest open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies...
- OpenRISC 1200OpenRISC 1200The OpenRISC 1200 is a synthesizable CPU core maintained by developers at OpenCores.org. The OR1200 design is an open source implementation of the OpenRISC 1000 RISC architecture . The Verilog RTL description is released under the GNU Lesser General Public License .-Architecture :The IP core of...
- Open Virtual Platforms
- OpenSPARCOpenSPARCOpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems' register-transfer level Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor. On 21 March 2006, Sun released the source code to the...
- LEONLEONLEON is a 32-bit CPU microprocessor core, based on the SPARC-V8 RISC architecture and instruction set. It was originally designed by the European Space Research and Technology Centre , part of the European Space Agency , and after that by Gaisler Research. It is described in synthesizable VHDL...
- LatticeMico32LatticeMico32LatticeMico32 is a 32-bit microprocessor soft core from Lattice Semiconductor optimized for field-programmable gate arrays . It uses a Harvard architecture, which means the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired.LatticeMico32...
External links
- OpenRISC main project page at the OpenCores Website
- GNU toolchain building guides
- Beyond Semiconductor commercial fabless semiconductor companyFabless semiconductor companyA fabless semiconductor company specializes in the design and sale of hardware devices and semiconductor chips while outsourcing the fabrication or "fab" of the devices to a specialized manufacturer called a semiconductor foundry...
founded by the developers of OpenRISC - Dynalith Systems company website.
- Imperas company website.
- Flextronics International company website
- Jennic company website
- ORSoC company website. ORSoC also maintain the opencores.org website.
- Eetimes article