PSE-36
Encyclopedia
In computing
, PSE-36 refers to a feature of x86 processors that extends the physical memory addressing capabilities from 32 bits to 36 bits. This mechanism is a simpler alternative to the Physical Address Extension
(PAE) method. It uses the Page Size Extension
(PSE) mode and a modified page directory table to map 4 megabyte
(MB) pages into a 64 gigabyte
(GiB
) physical address space. PSE-36 was introduced into the x86 with the Pentium III
architecture.
If newer PSE-36 capability is available on the CPU, as checked using the CPUID
instruction, then 4 more bits, in addition to the 10 bits used in PSE, are used inside a page directory entry pointing to a large page. This allows a large page to be located in 36 bit address space.
PAE
also allows 36-bit addressing. PSE-36 has the advantages that the hierarchy of page tables is not changed, and that page entries keep their old 32-bit format and are not extended to 64 bits. The obvious disadvantage of PSE-36 is that only large pages can be located in 64 GiB of physical memory, and small pages can still be located only in the first 4 GiB of physical memory.
The PS bit (bit 7) in the Page Directory Entry (PDE) denotes whether this entry refers to a page table (that describes 1024 4-KiB pages) or one 4 MiB page. PDE structures in normal mode, PSE mode, and PSE-36 mode are as follows:
PAT: Page Attribute Table (since Pentium III, must be zero for older CPUs) D: "dirty" bit: set to 1 by CPU if there was a write access to that page. For 4 KiB pages this flag exists in the according page table entry (PTE).
AMD extends this scheme to 40 address bits by interpreting bits 20..13 of a PDE as bit 39..32 of the page base address in their AMD64 processors, so only bit 21 is reserved (must be zero).
Computing
Computing is usually defined as the activity of using and improving computer hardware and software. It is the computer-specific part of information technology...
, PSE-36 refers to a feature of x86 processors that extends the physical memory addressing capabilities from 32 bits to 36 bits. This mechanism is a simpler alternative to the Physical Address Extension
Physical Address Extension
In computing, Physical Address Extension is a feature to allow x86 processors to access a physical address space larger than 4 gigabytes....
(PAE) method. It uses the Page Size Extension
Page Size Extension
In computing, Page Size Extension refers to a feature of x86 processors that allows for pages larger than the traditional 4 KiB size. It was introduced in the original Pentium processor, but it was only publicly documented by Intel with the release of the Pentium Pro. The CPUID instruction can be...
(PSE) mode and a modified page directory table to map 4 megabyte
Megabyte
The megabyte is a multiple of the unit byte for digital information storage or transmission with two different values depending on context: bytes generally for computer memory; and one million bytes generally for computer storage. The IEEE Standards Board has decided that "Mega will mean 1 000...
(MB) pages into a 64 gigabyte
Gigabyte
The gigabyte is a multiple of the unit byte for digital information storage. The prefix giga means 109 in the International System of Units , therefore 1 gigabyte is...
(GiB
Gib
Gib may refer to:* A castrated male cat or ferret* Gibibit , measurement unit of digitally stored computer information* Gibraltar, British overseas territory* Drywall, construction material...
) physical address space. PSE-36 was introduced into the x86 with the Pentium III
Pentium III
The Pentium III brand refers to Intel's 32-bit x86 desktop and mobile microprocessors based on the sixth-generation P6 microarchitecture introduced on February 26, 1999. The brand's initial processors were very similar to the earlier Pentium II-branded microprocessors...
architecture.
Operation
Enabling PSE alone (by setting bit 4, PSE, of the system registerCR4) allows to use large 4 MiB pages along with normal 4 KiB pages.If newer PSE-36 capability is available on the CPU, as checked using the CPUID
CPUID
The CPUID opcode is a processor supplementary instruction for the x86 architecture. It was introduced by Intel in 1993 when it introduced the Pentium and SL-Enhanced 486 processors....
instruction, then 4 more bits, in addition to the 10 bits used in PSE, are used inside a page directory entry pointing to a large page. This allows a large page to be located in 36 bit address space.
PAE
Physical Address Extension
In computing, Physical Address Extension is a feature to allow x86 processors to access a physical address space larger than 4 gigabytes....
also allows 36-bit addressing. PSE-36 has the advantages that the hierarchy of page tables is not changed, and that page entries keep their old 32-bit format and are not extended to 64 bits. The obvious disadvantage of PSE-36 is that only large pages can be located in 64 GiB of physical memory, and small pages can still be located only in the first 4 GiB of physical memory.
The PS bit (bit 7) in the Page Directory Entry (PDE) denotes whether this entry refers to a page table (that describes 1024 4-KiB pages) or one 4 MiB page. PDE structures in normal mode, PSE mode, and PSE-36 mode are as follows:
| 31-22 | 21-17 | 16-13 | 12 | 11-9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| non-PSE | base address of page table | avail | 0 | PS=0 | ign | A | PCD | PWT | U | W | P | |||||||||||||||||||||
| PSE | bit 31..22 of page frame address | reserved (must be zero) | PAT | avail | 0 | PS=1 | D | A | PCD | PWT | U | W | P | |||||||||||||||||||
| PSE-36 | bit 31..22 of page frame address | reserved (must be zero) | bit 35..32 of page frame address | PAT | avail | 0 | PS=1 | D | A | PCD | PWT | U | W | P | ||||||||||||||||||
PAT: Page Attribute Table (since Pentium III, must be zero for older CPUs) D: "dirty" bit: set to 1 by CPU if there was a write access to that page. For 4 KiB pages this flag exists in the according page table entry (PTE).
AMD extends this scheme to 40 address bits by interpreting bits 20..13 of a PDE as bit 39..32 of the page base address in their AMD64 processors, so only bit 21 is reserved (must be zero).