Page Size Extension
Encyclopedia
In computing
, Page Size Extension (PSE) refers to a feature of x86 processors that allows for pages
larger than the traditional 4 KiB
size. It was introduced in the original Pentium processor, but it was only publicly documented by Intel with the release of the Pentium Pro
. The CPUID
instruction can be used to identify the availability of PSE on x86 CPUs.
memory block. In order to fulfill this request, an operating system that supports paging and that is running on older x86 CPUs will have to allocate 256 pages
of 4 KiB each. An overhead of 1 KiB of memory is required for maintaining page directories and page tables.
When accessing this 1 MiB memory, each of the 256 page entries would be cached in the TLB
(a cache that remembers virtual address to physical address translations for faster lookup on subsequent memory requests). Cluttering the TLB is possibly one of the largest downsides of having several page entries for what could have been allocated in one single memory block. If the TLB gets filled, then a TLB entry would have to be freed, the page directory and page tables would have to be “walked” in memory, and finally, the memory would be accessed and the new entry would be brought into the TLB. This is a severe performance penalty and it is possibly the largest motivation for augmenting the x86 architecture with larger page sizes.
The PSE allows for page sizes of 4 MiB to exist along with 4 KiB pages. The 1 MiB request described previously would easily be fulfilled with a single 4 MiB page, and it would require only one TLB entry. However, the downside of using larger page sizes is internal fragmentation
.
In traditional 32-bit protected mode
, x86 processors use a two-level page translation scheme, where the control register
s, similarly consisting of 1024 x 4 byte entries pointing to 4 KiB long pages
.
Enabling PSE (by setting bit 4, PSE, of the system register
If newer PSE-36
capability is available on the CPU, as checked using the CPUID
instruction, then 4 more bits, in addition to normal 10 bits, are used inside a page directory entry pointing to a large page. This allows a large page to be located in 36 bit address space.
If PSE is used together with PAE
the size of the pages is reduced from 4 MiB to 2 MiB.
Computing
Computing is usually defined as the activity of using and improving computer hardware and software. It is the computer-specific part of information technology...
, Page Size Extension (PSE) refers to a feature of x86 processors that allows for pages
Page (computing)
A page, memory page, or virtual page is a fixed-length contiguous block of virtual memory that is the smallest unit of data for the following:* memory allocation performed by the operating system for a program; and...
larger than the traditional 4 KiB
Kibibyte
The kibibyte is a multiple of the unit byte for quantities of digital information. The binary prefix kibi means 1024; therefore, 1 kibibyte is . The unit symbol for the kibibyte is KiB. The unit was established by the International Electrotechnical Commission in 1999 and has been accepted for use...
size. It was introduced in the original Pentium processor, but it was only publicly documented by Intel with the release of the Pentium Pro
Pentium Pro
The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel introduced in November 1, 1995 . It introduced the P6 microarchitecture and was originally intended to replace the original Pentium in a full range of applications...
. The CPUID
CPUID
The CPUID opcode is a processor supplementary instruction for the x86 architecture. It was introduced by Intel in 1993 when it introduced the Pentium and SL-Enhanced 486 processors....
instruction can be used to identify the availability of PSE on x86 CPUs.
Motivation
Imagine the following scenario. An application program requests a 1 MiBMebibyte
The mebibyte is a multiple of the unit byte for digital information. The binary prefix mebi means 220, therefore 1 mebibyte is . The unit symbol for the mebibyte is MiB. The unit was established by the International Electrotechnical Commission in 2000 and has been accepted for use by all major...
memory block. In order to fulfill this request, an operating system that supports paging and that is running on older x86 CPUs will have to allocate 256 pages
Pages
Pages is a word processor and page layout application developed by Apple. It is part of the iWork productivity suite and runs on the Mac OS X & iOS operating systems. The first version of Pages was announced on January 11, 2005, and was released one month later. The most recent Macintosh version,...
of 4 KiB each. An overhead of 1 KiB of memory is required for maintaining page directories and page tables.
When accessing this 1 MiB memory, each of the 256 page entries would be cached in the TLB
Translation Lookaside Buffer
A translation lookaside buffer is a CPU cache that memory management hardware uses to improve virtual address translation speed. All current desktop and server processors use a TLB to map virtual and physical address spaces, and it is ubiquitous in any hardware which utilizes virtual memory.The...
(a cache that remembers virtual address to physical address translations for faster lookup on subsequent memory requests). Cluttering the TLB is possibly one of the largest downsides of having several page entries for what could have been allocated in one single memory block. If the TLB gets filled, then a TLB entry would have to be freed, the page directory and page tables would have to be “walked” in memory, and finally, the memory would be accessed and the new entry would be brought into the TLB. This is a severe performance penalty and it is possibly the largest motivation for augmenting the x86 architecture with larger page sizes.
The PSE allows for page sizes of 4 MiB to exist along with 4 KiB pages. The 1 MiB request described previously would easily be fulfilled with a single 4 MiB page, and it would require only one TLB entry. However, the downside of using larger page sizes is internal fragmentation
Fragmentation (computer)
In computer storage, fragmentation is a phenomenon in which storage space is used inefficiently, reducing storage capacity and in most cases reducing the performance. The term is also used to denote the wasted space itself....
.
Operation
Protected mode
In computing, protected mode, also called protected virtual address mode, is an operational mode of x86-compatible central processing units...
, x86 processors use a two-level page translation scheme, where the control register
Control register
A control register is a processor register which changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.-CR0:The CR0 register is 32 bits...
CR3 points to a single 4 KiB long page directory, which is divided into 1024 x 4 byte entries that point to 4 KiB long page tablePage table
A page table is the data structure used by a virtual memory system in a computer operating system to store the mapping between virtual addresses and physical addresses. Virtual addresses are those unique to the accessing process...
s, similarly consisting of 1024 x 4 byte entries pointing to 4 KiB long pages
Page (computing)
A page, memory page, or virtual page is a fixed-length contiguous block of virtual memory that is the smallest unit of data for the following:* memory allocation performed by the operating system for a program; and...
.
Enabling PSE (by setting bit 4, PSE, of the system register
CR4) changes this scheme. The entries in the page directory have an additional flag, in bit 7, named PS (for Page Size). This flag was ignored without PSE, but now, the page directory entry with PS set to 1 does not point to a page table, but to a single large 4 MiB page. The page directory entry with PS set to 0 behaves as without PSE.If newer PSE-36
PSE-36
In computing, PSE-36 refers to a feature of x86 processors that extends the physical memory addressing capabilities from 32 bits to 36 bits. This mechanism is a simpler alternative to the Physical Address Extension method. It uses the Page Size Extension mode and a modified page directory table...
capability is available on the CPU, as checked using the CPUID
CPUID
The CPUID opcode is a processor supplementary instruction for the x86 architecture. It was introduced by Intel in 1993 when it introduced the Pentium and SL-Enhanced 486 processors....
instruction, then 4 more bits, in addition to normal 10 bits, are used inside a page directory entry pointing to a large page. This allows a large page to be located in 36 bit address space.
If PSE is used together with PAE
Physical Address Extension
In computing, Physical Address Extension is a feature to allow x86 processors to access a physical address space larger than 4 gigabytes....
the size of the pages is reduced from 4 MiB to 2 MiB.