Property Specification Language
Encyclopedia
Property Specification Language (PSL) is a language developed by Accellera
for specifying properties
or assertions
about hardware
designs. The properties can then be simulated
or formally verified
. Since September 2004 the standard
ization on the language has been done in IEEE 1850 working group. In September 2005, the IEEE 1850 Standard for Property Specification Language (PSL) was announced.
Property Specification Language aims to be used with multiple electronic system design languages such as:
Accellera
Accellera is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation and IC design and manufacturing. It is less constrained than the IEEE and is therefore the starting place for many standards. Once...
for specifying properties
Property (philosophy)
In modern philosophy, logic, and mathematics a property is an attribute of an object; a red object is said to have the property of redness. The property may be considered a form of object in its own right, able to possess other properties. A property however differs from individual objects in that...
or assertions
Assertion (computing)
In computer programming, an assertion is a predicate placed in a program to indicate that the developer thinks that the predicate is always true at that place.For example, the following code contains two assertions:...
about hardware
Hardware
Hardware is a general term for equipment such as keys, locks, hinges, latches, handles, wire, chains, plumbing supplies, tools, utensils, cutlery and machine parts. Household hardware is typically sold in hardware stores....
designs. The properties can then be simulated
Simulation
Simulation is the imitation of some real thing available, state of affairs, or process. The act of simulating something generally entails representing certain key characteristics or behaviours of a selected physical or abstract system....
or formally verified
Formal verification
In the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics .- Usage :Formal verification can be...
. Since September 2004 the standard
Standardization
Standardization is the process of developing and implementing technical standards.The goals of standardization can be to help with independence of single suppliers , compatibility, interoperability, safety, repeatability, or quality....
ization on the language has been done in IEEE 1850 working group. In September 2005, the IEEE 1850 Standard for Property Specification Language (PSL) was announced.
Property Specification Language aims to be used with multiple electronic system design languages such as:
- VHDL (IEEE 1076),
- VerilogVerilogIn the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
(IEEE 1364), - System Verilog (IEEE 1800), and
- SystemCSystemCSystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...
(IEEE 1666) by OSCIOsciThe Osci , were an Italic people of Campania and Latium adiectum during Roman times. They spoke the Oscan language, also spoken by the Samnites of Southern Italy. Although the language of the Samnites was called Oscan, the Samnites were never called Osci, or the Osci Samnites...
.