QorIQ
Encyclopedia
QorIQ is a brand of Power Architecture
-based communications microprocessor
s from Freescale. It is the evolutionary step from the PowerQUICC
platform and will be built around one or more Power Architecture e500mc
cores and come in five different product platforms, P1, P2, P3, P4 and P5, segmented by performance and functionality. The platform keeps software compatibility with older PowerPC
products such as the PowerQUICC platform.
The QorIQ brand and the P1, P2 and P4 product families were announced in June 2008. Details of P3 and P5 products were announced in 2010.
QorIQ P Series processors will be manufactured on a 45 nm fabrication process and was available in the end of 2008 (P1 and P2), mid 2009 (P4) and 2010 (P5). The roadmap stretched beyond the 28 nm process, and all are pushing a very aggressive power envelope target, capping at 30 W
.
data/instruction L1 cache, 36-bit physical memory addressing [appended to the top of the virtual address in the process context, each process is still 32bit], a double precision
floating point unit
is present on some cores (not all) and support for virtualization
through a hypervisor
layer is present in products featuring the e500mc or the e5500. The dual and multi-core devices supports both symmetric
and asymmetric
multiprocessing
, and can run multiple operating systems in parallel.
controllers, two USB 2.0 controllers, a security engine, a 32-bit DDR2
and DDR3 memory controller with ECC support, dual four-channel DMA
controllers, a SD
/MMC
host controller and high speed interfaces which can be configured as SerDes
lanes, PCIe and SGMII interfaces. The chip is packaged in 689-pin packages which are pin compatible with the P2 family processors.
controllers, a USB 2.0 controller, a 64-bit DDR2
and DDR3 memory controller with ECC support, dual four-channel DMA
controllers, a SD
/MMC
host controller and high speed SerDes
lanes which can be configured as three PCIe interfaces, two RapidIO
interfaces and two SGMII interfaces. The chips are packaged in 689-pin packages which are pin compatible with the P1 family processors.
and routing. The P3 family offers a multi-core platform, with support for up to four Power Architecture e500mc
cores at frequencies up to 1.5 GHz on the same chip, connected by the CoreNet coherency fabric. The chips include among other integrated functionality, integrated L3 caches, memory controller, multiple I/O-devices such as DUART
, GPIO
and USB 2.0, security and encryption engines, a queue manager scheduling on-chip events and a SerDes based on-chip high speed network configurable as multiple Gigabit Ethernet, 10 Gigabit Ethernet
, RapidIO or PCIe interfaces.http://cache.freescale.com/files/32bit/doc/fact_sheet/QP3041FS.pdf?fpsp=1&WT_TYPE=Fact%20Sheets&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation
The P3 family processors share the same physical package with, and are also software backwards compatible with, P4 and P5. The P3 processors have 1.3 GHz 64-bit DDR3 memory controllers, 18 SerDes lanes for networking, hardware accelerators for packet handling and scheduling, regular expressions, RAID, security, cryptography and RapidIO.
The cores are supported by a hardware hypervisor and can be run in symmetric or asymmetric mode meaning that the cores can run and boot operating systems together or separately, resetting and partitioning cores and datapaths independently without disturbing other operating systems and applications.
ing and enterprise level switching
and routing. The P4 family offers an extreme multi-core platform, with support for up to eight Power Architecture e500mc
cores at frequencies up to 1.5 GHz on the same chip, connected by the CoreNet coherency fabric. The chips include among other integrated functionality, integrated L3 caches, memory controllers, multiple I/O-devices such as DUART
, GPIO
and USB 2.0, security and encryption engines, a queue manager scheduling on-chip events and a SerDes based on-chip high speed network configurable as multiple Gigabit Ethernet, 10 Gigabit Ethernet
, RapidIO or PCIe interfaces.
The cores are supported by a hardware hypervisor and can be run in symmetric or asymmetric mode meaning that the cores can run and boot operating systems together or separately, resetting and partitioning cores and datapaths independently without disturbing other operating systems and applications.
To help software developers and system designers get started with the QorIQ P4080, Freescale worked with Virtutech
to create a virtual platform for the P4080 that can be used prior to silicon availability to develop, test, and debug software for the chip. Currently, the simulator is only for the P4080, not the other chips announced in 2008.
Because of its complete set of network engines, this processor can be used for telecommunication systems (LTE eNodeB, EPC, WCDMA, BTS), so Freescale and 6WIND ported 6WIND's packet processing software to the P4080.
e5500
core scaling up to 2.5 GHz and allowing numerous auxiliary application processing units as well as multi core operation via the CoreNet fabric. The P5 series processors share the same physical package and a is also software backwards compatible with P3 and P4. The P5 processors have 1.3 GHz 64-bit DDR3 memory controllers, 18 SerDes lanes for networking, hardware accelerators for packet handling and scheduling, regular expressions, RAID, security, cryptography and RapidIO.
Introduced in June 2010, samples will be available late 2010 and full production is expected in 2011.
Applications rage from high end networking control plane infrastructure, high end storage networking and complex military and industrial devices.
SoC processors targeted wireless infrastructure applications. The PSC913x family chips uses an e500 core based CPU and StarCore SC3850 DSPs will be available in 2011, and is manufactured on a 45 nm process, with 28 nm parts on the roadmap for more demanding applications.
with integrated AltiVec
SIMD
processing units. Products will range from single core versions up to parts with 12 cores or more with frequencies ranging all the way up to 2.5 GHz. The processes will be sectioned into five classes according to performance and features, named T1 through T5, and will be manufactured in a 28 nm process beginning in 2012.
Freescale has partnered with networking company 6WIND
to provide software developers with a high-performance commercial packet processing solution for the QorIQ platform.
Power Architecture
Power Architecture is a broad term to describe similar RISC instruction sets for microprocessors developed and manufactured by such companies as IBM, Freescale, AMCC, Tundra and P.A. Semi...
-based communications microprocessor
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
s from Freescale. It is the evolutionary step from the PowerQUICC
PowerQUICC
PowerQUICC is the name for several Power Architecture based microcontrollers from Freescale Semiconductor. They are built around one or more PowerPC cores and the QUICC Engine which is a separate RISC core specialized in such tasks such as I/O, communications, ATM, security acceleration, networking...
platform and will be built around one or more Power Architecture e500mc
PowerPC e500
The PowerPC e500 is a 32-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core is compatible with the older PowerPC Book E specification as well as the Power ISA v.2.03. It has a dual issue, seven-stage pipeline with FPUs , 32/32 KiB data and instruction L1 caches...
cores and come in five different product platforms, P1, P2, P3, P4 and P5, segmented by performance and functionality. The platform keeps software compatibility with older PowerPC
PowerPC
PowerPC is a RISC architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM...
products such as the PowerQUICC platform.
The QorIQ brand and the P1, P2 and P4 product families were announced in June 2008. Details of P3 and P5 products were announced in 2010.
QorIQ P Series processors will be manufactured on a 45 nm fabrication process and was available in the end of 2008 (P1 and P2), mid 2009 (P4) and 2010 (P5). The roadmap stretched beyond the 28 nm process, and all are pushing a very aggressive power envelope target, capping at 30 W
Watt
The watt is a derived unit of power in the International System of Units , named after the Scottish engineer James Watt . The unit, defined as one joule per second, measures the rate of energy conversion.-Definition:...
.
P Series
The QorIQ P Series processors are based on Power Architecture e500 or e5500 cores. The P10xx and P20xx series are based on the e500v2 core, P30xx and P40xx on the e500mc core, and P50xx on the e5500 core. Features include 32/32 kBKilobyte
The kilobyte is a multiple of the unit byte for digital information. Although the prefix kilo- means 1000, the term kilobyte and symbol KB have historically been used to refer to either 1024 bytes or 1000 bytes, dependent upon context, in the fields of computer science and information...
data/instruction L1 cache, 36-bit physical memory addressing [appended to the top of the virtual address in the process context, each process is still 32bit], a double precision
Double precision
In computing, double precision is a computer number format that occupies two adjacent storage locations in computer memory. A double-precision number, sometimes simply called a double, may be defined to be an integer, fixed point, or floating point .Modern computers with 32-bit storage locations...
floating point unit
Floating point unit
A floating-point unit is a part of a computer system specially designed to carry out operations on floating point numbers. Typical operations are addition, subtraction, multiplication, division, and square root...
is present on some cores (not all) and support for virtualization
Full virtualization
In computer science, full virtualization is a virtualization technique used to provide a certain kind of virtual machine environment, namely, one that is a complete simulation of the underlying hardware...
through a hypervisor
Hypervisor
In computing, a hypervisor, also called virtual machine manager , is one of many hardware virtualization techniques that allow multiple operating systems, termed guests, to run concurrently on a host computer. It is so named because it is conceptually one level higher than a supervisory program...
layer is present in products featuring the e500mc or the e5500. The dual and multi-core devices supports both symmetric
Symmetric multiprocessing
In computing, symmetric multiprocessing involves a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance. Most common multiprocessor systems today use an SMP architecture...
and asymmetric
Asymmetric multiprocessing
Asymmetric multiprocessing, or AMP, was a software stopgap for handling multiple CPUs before symmetric multiprocessing, or SMP, was available.Multiprocessing is the use of more than one CPU in a computer system...
multiprocessing
Multiprocessing
Multiprocessing is the use of two or more central processing units within a single computer system. The term also refers to the ability of a system to support more than one processor and/or the ability to allocate tasks between them...
, and can run multiple operating systems in parallel.
P1
The P1 series is tailored for gateways, Ethernet switches, wireless LAN access points, and general-purpose control applications. It is the entry level platform, ranging from 400 to 800 MHz devices. It is designed to replace the PowerQUICC II Pro and PowerQUICC III platforms. The chips include among other integrated functionality, Gigabit EthernetGigabit Ethernet
Gigabit Ethernet is a term describing various technologies for transmitting Ethernet frames at a rate of a gigabit per second , as defined by the IEEE 802.3-2008 standard. It came into use beginning in 1999, gradually supplanting Fast Ethernet in wired local networks where it performed...
controllers, two USB 2.0 controllers, a security engine, a 32-bit DDR2
DDR2 SDRAM
DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
and DDR3 memory controller with ECC support, dual four-channel DMA
Direct memory access
Direct memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....
controllers, a SD
Secure Digital card
Secure Digital is a non-volatile memory card format developed by the SD Card Association for use in portable devices. The SD technology is used by more than 400 brands across dozens of product categories and more than 8,000 models, and is considered the de-facto industry standard.Secure Digital...
/MMC
MultiMediaCard
The MultiMediaCard is a flash memory memory card standard. Unveiled in 1997 by Siemens AG and SanDisk, it is based on Toshiba's NAND-based flash memory, and is therefore much smaller than earlier systems based on Intel NOR-based memory such as CompactFlash. MMC is about the size of a postage...
host controller and high speed interfaces which can be configured as SerDes
SerDes
A Serializer/Deserializer is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction...
lanes, PCIe and SGMII interfaces. The chip is packaged in 689-pin packages which are pin compatible with the P2 family processors.
- P1011 – Includes one 800 MHz e500 core, 256 kB L2 cache, four SerDes lanes, three Gbit Ethernet controllers and a TDM engineTime-division multiplexingTime-division multiplexing is a type of digital multiplexing in which two or more bit streams or signals are transferred apparently simultaneously as sub-channels in one communication channel, but are physically taking turns on the channel. The time domain is divided into several recurrent...
for legacy phone applications. - P1020 – includes two 800 MHz e500 cores, 256 kB shared L2 cache, four SerDes lanes, three Gbit Ethernet controllers and a TDM engine.
- Freescale announces pin-compatible, power-efficient series in new QorIQ communications platforms – Freescale.com
- P1 Series Single- and Dual-Core Communications Processors – Freescale.com
P2
The P2 series is designed for a wide variety of applications in the networking, telecom, military and industrial markets. It will be available in special high quality parts, with junction tolerances from -40 to 125 °C, especially suited for demanding out doors environments. It is the mid-level platform, with devices ranging from 800 MHz up to 1.2 GHz. It is designed to replace the PowerQUICC II Pro and PowerQUICC III platforms. The chips include, among other integrated functionality, a 512 kB L2 cache, a security engine, three Gigabit EthernetGigabit Ethernet
Gigabit Ethernet is a term describing various technologies for transmitting Ethernet frames at a rate of a gigabit per second , as defined by the IEEE 802.3-2008 standard. It came into use beginning in 1999, gradually supplanting Fast Ethernet in wired local networks where it performed...
controllers, a USB 2.0 controller, a 64-bit DDR2
DDR2 SDRAM
DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
and DDR3 memory controller with ECC support, dual four-channel DMA
Direct memory access
Direct memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....
controllers, a SD
Secure Digital card
Secure Digital is a non-volatile memory card format developed by the SD Card Association for use in portable devices. The SD technology is used by more than 400 brands across dozens of product categories and more than 8,000 models, and is considered the de-facto industry standard.Secure Digital...
/MMC
MultiMediaCard
The MultiMediaCard is a flash memory memory card standard. Unveiled in 1997 by Siemens AG and SanDisk, it is based on Toshiba's NAND-based flash memory, and is therefore much smaller than earlier systems based on Intel NOR-based memory such as CompactFlash. MMC is about the size of a postage...
host controller and high speed SerDes
SerDes
A Serializer/Deserializer is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction...
lanes which can be configured as three PCIe interfaces, two RapidIO
RapidIO
The RapidIO architecture is a high-performance packet-switched, interconnect technology for interconnecting chips on a circuit board, and also circuit boards to each other using a backplane...
interfaces and two SGMII interfaces. The chips are packaged in 689-pin packages which are pin compatible with the P1 family processors.
- P2010 – Includes one 1.2 GHz core
- P2020 – Includes two 1.2 GHz cores, with shared L2 cache
- Freescale announces pin-compatible, power-efficient series in new QorIQ communications platforms – Freescale.com
- P2 Series Single- and dual-core communications processors – Freescale.com
- P2040
- P2041
P3
The P3 series is a mid performance networking platform, designed for switchingNetwork switch
A network switch or switching hub is a computer networking device that connects network segments.The term commonly refers to a multi-port network bridge that processes and routes data at the data link layer of the OSI model...
and routing. The P3 family offers a multi-core platform, with support for up to four Power Architecture e500mc
PowerPC e500
The PowerPC e500 is a 32-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core is compatible with the older PowerPC Book E specification as well as the Power ISA v.2.03. It has a dual issue, seven-stage pipeline with FPUs , 32/32 KiB data and instruction L1 caches...
cores at frequencies up to 1.5 GHz on the same chip, connected by the CoreNet coherency fabric. The chips include among other integrated functionality, integrated L3 caches, memory controller, multiple I/O-devices such as DUART
Universal asynchronous receiver/transmitter
A universal asynchronous receiver/transmitter, abbreviated UART , is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as EIA RS-232, RS-422 or...
, GPIO
GPIO
General Purpose Input/Output is a generic pin on a chip whose behavior can be controlled through software....
and USB 2.0, security and encryption engines, a queue manager scheduling on-chip events and a SerDes based on-chip high speed network configurable as multiple Gigabit Ethernet, 10 Gigabit Ethernet
10 Gigabit Ethernet
The 10 gigabit Ethernet computer networking standard was first published in 2002. It defines a version of Ethernet with a nominal data rate of 10 Gbit/s , ten times faster than gigabit Ethernet.10 gigabit Ethernet defines only full duplex point to point links which are generally connected by...
, RapidIO or PCIe interfaces.http://cache.freescale.com/files/32bit/doc/fact_sheet/QP3041FS.pdf?fpsp=1&WT_TYPE=Fact%20Sheets&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation
The P3 family processors share the same physical package with, and are also software backwards compatible with, P4 and P5. The P3 processors have 1.3 GHz 64-bit DDR3 memory controllers, 18 SerDes lanes for networking, hardware accelerators for packet handling and scheduling, regular expressions, RAID, security, cryptography and RapidIO.
The cores are supported by a hardware hypervisor and can be run in symmetric or asymmetric mode meaning that the cores can run and boot operating systems together or separately, resetting and partitioning cores and datapaths independently without disturbing other operating systems and applications.
- P3041 - Quad 1.5 GHz cores, 128 kB L2 cache per core, single 1.3 GHz 64-bit DDR3 controller. Manufactured on a 45 nm process operating in a 12W envelope.
P4
The P4 series is a high performance networking platform, designed for backbone networkBackbone network
A backbone network or network backbone is a part of computer network infrastructure that interconnects various pieces of network, providing a path for the exchange of information between different LANs or subnetworks. A backbone can tie together diverse networks in the same building, in different...
ing and enterprise level switching
Network switch
A network switch or switching hub is a computer networking device that connects network segments.The term commonly refers to a multi-port network bridge that processes and routes data at the data link layer of the OSI model...
and routing. The P4 family offers an extreme multi-core platform, with support for up to eight Power Architecture e500mc
PowerPC e500
The PowerPC e500 is a 32-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core is compatible with the older PowerPC Book E specification as well as the Power ISA v.2.03. It has a dual issue, seven-stage pipeline with FPUs , 32/32 KiB data and instruction L1 caches...
cores at frequencies up to 1.5 GHz on the same chip, connected by the CoreNet coherency fabric. The chips include among other integrated functionality, integrated L3 caches, memory controllers, multiple I/O-devices such as DUART
Universal asynchronous receiver/transmitter
A universal asynchronous receiver/transmitter, abbreviated UART , is a type of "asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as EIA RS-232, RS-422 or...
, GPIO
GPIO
General Purpose Input/Output is a generic pin on a chip whose behavior can be controlled through software....
and USB 2.0, security and encryption engines, a queue manager scheduling on-chip events and a SerDes based on-chip high speed network configurable as multiple Gigabit Ethernet, 10 Gigabit Ethernet
10 Gigabit Ethernet
The 10 gigabit Ethernet computer networking standard was first published in 2002. It defines a version of Ethernet with a nominal data rate of 10 Gbit/s , ten times faster than gigabit Ethernet.10 gigabit Ethernet defines only full duplex point to point links which are generally connected by...
, RapidIO or PCIe interfaces.
The cores are supported by a hardware hypervisor and can be run in symmetric or asymmetric mode meaning that the cores can run and boot operating systems together or separately, resetting and partitioning cores and datapaths independently without disturbing other operating systems and applications.
- P4080 – Includes eight e500mc cores, each with 32/32kB instruction/data L1 caches and a 128 kB L2 cache. The chip has dual 1 MB L3 caches, each connected to a 64-bit DDR2/DDR3 memory controller. The chip contains a security and encryption module, capable of packet parsing and classification, and acceleration of encryption and regexp pattern matching. The chip can be configured with up to eight Gigabit and two 10 Gigabit Ethernet controllers, three 5 GHz PCIe ports and two RapidIO interfaces. It also has various other peripheral connectivity such as two USB2 controllers. It is designed to operate below 30 W at 1.5 GHz. The processor is manufactured on a 45 nm SOI process and begun sampling to customers in August 2009.
- Eight-core microprocessor from Freescale redefines state-of-the-art for embedded multicore processing – Freescale.com
- P4 Series P4080 multicore processor – Freescale.com
To help software developers and system designers get started with the QorIQ P4080, Freescale worked with Virtutech
Virtutech
Virtutech was founded in 1998 as a spin-off from the Swedish Institute of Computer Science , in Stockholm, Sweden. In 2004, the headquarters was moved to San Jose, California, USA. The Stockholm site remains the company's R&D center. The company's main product is Simics software, used by teams of...
to create a virtual platform for the P4080 that can be used prior to silicon availability to develop, test, and debug software for the chip. Currently, the simulator is only for the P4080, not the other chips announced in 2008.
Because of its complete set of network engines, this processor can be used for telecommunication systems (LTE eNodeB, EPC, WCDMA, BTS), so Freescale and 6WIND ported 6WIND's packet processing software to the P4080.
P5
The P5 series is based on the high performance 64-bit64-bit
64-bit is a word size that defines certain classes of computer architecture, buses, memory and CPUs, and by extension the software that runs on them. 64-bit CPUs have existed in supercomputers since the 1970s and in RISC-based workstations and servers since the early 1990s...
e5500
PowerPC e5500
The PowerPC e5500 is a 64-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core is compatible with the Power ISA v.2.06 with hypervisor support. It has a four issue, seven-stage out-of-order pipeline with a double precision FPU, three Integer units, 32/32 KB data...
core scaling up to 2.5 GHz and allowing numerous auxiliary application processing units as well as multi core operation via the CoreNet fabric. The P5 series processors share the same physical package and a is also software backwards compatible with P3 and P4. The P5 processors have 1.3 GHz 64-bit DDR3 memory controllers, 18 SerDes lanes for networking, hardware accelerators for packet handling and scheduling, regular expressions, RAID, security, cryptography and RapidIO.
Introduced in June 2010, samples will be available late 2010 and full production is expected in 2011.
Applications rage from high end networking control plane infrastructure, high end storage networking and complex military and industrial devices.
- P5010 - Singe e5500 2.2 GHz core, 1 MB L3 cache, single DDR3 controller, manufactured on a 45 nm process and operating in a 30W envelope.
- P5020 - Dual e5500 2.2 GHz cores, dual 1 MB L3 caches, dual DDR3 controllers, manufactured on a 45 nm process and operating in a 30W envelope.
Qonverge
In February 2011 Freescale introduced the QorIQ Qonverge platform which is a series of combined CPU and DSPDigital signal processor
A digital signal processor is a specialized microprocessor with an architecture optimized for the fast operational needs of digital signal processing.-Typical characteristics:...
SoC processors targeted wireless infrastructure applications. The PSC913x family chips uses an e500 core based CPU and StarCore SC3850 DSPs will be available in 2011, and is manufactured on a 45 nm process, with 28 nm parts on the roadmap for more demanding applications.
AMP Series
The QorIQ Advanced Multiprocessing, AMP Series, processors are all based on the multithreaded 64-bit e6500 corePowerPC e6500
The PowerPC e6500 is a multithreaded 64-bit Power Architecture-based microprocessor core from Freescale Semiconductor. e6500 will power the entire range of QorIQ AMP Series system on a chip processors which share the common naming scheme: "Txxxx"...
with integrated AltiVec
AltiVec
AltiVec is a floating point and integer SIMD instruction set designed and owned by Apple, IBM and Freescale Semiconductor, formerly the Semiconductor Products Sector of Motorola, , and implemented on versions of the PowerPC including Motorola's G4, IBM's G5 and POWER6 processors, and P.A. Semi's...
SIMD
SIMD
Single instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously...
processing units. Products will range from single core versions up to parts with 12 cores or more with frequencies ranging all the way up to 2.5 GHz. The processes will be sectioned into five classes according to performance and features, named T1 through T5, and will be manufactured in a 28 nm process beginning in 2012.
T4
- T4240 – The first product announced and will incorporate twelve e6500 dual-threaded cores, four memory controllers and various other accelerators.
Networking, IT and telecommunication systems
The QorIQ products bring some new challenges in order to design some control planes of telecommunication systems and their data plane. For instance, when 4 or 8 cores are used, such as the P4080, in order to achieve millions of Packet Processing per seconds, the system does not scale with regular software stack because so many cores require a different system design. In order to restore simplicity and still get the highest level of performance, the telecommunication systems are based on a segregation of the cores. Some cores are used for the control plane while some others are used for a re-designed data plane based on a Fast Path.Freescale has partnered with networking company 6WIND
6WIND
6WIND S.A. is a privately held company that provides packet processing software used by OEM companies to meet both the wire-speed performance and time-to-market requirements of mobile infrastructure, network security, high-frequency trading and deep packet inspection applications...
to provide software developers with a high-performance commercial packet processing solution for the QorIQ platform.
External links
- Freescale QorIQ communications platforms signal a new way forward for embedded multicore technology - Freescale.com
- Freescale's QorIQ website
- QorIQ moves Power architecture to multicore – EDN.com
- MontaVista: multicore Linux support for Freescale QorIQ P4080 – EmbeddedControlEurope.com
- QorIQ 45-nm communications MPUs feature dual cores, low power – ElectronicProducts.com
- Virtutech Enables Multi-Core Development Ecosystem for Freescale Power Architecture QorIQ P4080 Processor – TradingMarkets.com
- MontaVista Provides First No-Cost Evaluation of Commercial Linux for Freescale QorIQ P4080 Multicore Processor – Money.AOL.com
- Halfhill, Tom R. (7 July 2008). "Freescale's Multicore Makeover". Microprocessor Report.