Resolution enhancement technologies
Encyclopedia
Resolution enhancement technologies are methods used to modify photomask
s for integrated circuits (ICs) to compensate for limitations in the lithographic processes
used to manufacture the chips.
Traditionally, after an IC design has been converted into a physical layout
, the timing verified
, and the polygons certified to be DRC-clean
, the IC was ready for fabrication. The data files representing the various layers were shipped to a mask shop, which used mask-writing equipment to convert each data layer into a corresponding mask, and the masks were shipped to the fab where they were used to repeatedly manufacture the designs in silicon. In the past, the creation of the IC layout was the end of the involvement of electronic design automation
.
However, as Moore’s law has driven features to ever-smaller dimensions, new physical effects that could be effectively ignored in the past are now having an impact on the features that are formed on the silicon wafer. So even though the final layout may represent what is desired in silicon, the layout can still undergo dramatic alteration through several EDA tools before the masks are fabricated and shipped.
These alterations are required not to make any change in the device as designed, but to simply allow the manufacturing equipment, often purchased and optimized for making ICs one or two generations behind, to deliver the new devices. These alterations can be classed as being of two types.
The first type is distortion corrections, namely pre-compensating for distortions inherent in the manufacturing process, be it from a processing step, such as: photolithography
, etching, planarization, and deposition. These distortions are measured and a suitable model fitted, compensation is carried out usually using a rule or model based algorithm. When applied to printing distortions during photolithography, this distortion compensation is known as Optical Proximity Correction
(OPC).
The second type of Reticle Enhancement involves actually improving the manufacturability or resolution of the process. Examples of this include:
For each of these manufacturability improvement techniques there are certain layouts that either cannot be improved or cause issues in printing. These are classed as non-compliant layouts. These are avoided either at the design stage - using, for instance, Radically Restrictive Design Rules and/or creating addition DRC checks if appropriate. Both the lithographic compensations and manufacturability improvements are usually grouped under the heading resolution enhancement techniques (RET). Such techniques have been used since the 180nm node and have become more aggressively used as minimum feature size as dropped significantly below that of the imaging wavelength, currently limited to 193 nm.
This is closely related to, and a part of, the more general category of design for manufacturability (IC)
or DFM.
After RET, the next step in an EDA flow is usually mask data preparation
.
Photomask
A photomask is an opaque plate with holes or transparencies that allow light to shine through in a defined pattern. They are commonly used in photolithography.-Overview:...
s for integrated circuits (ICs) to compensate for limitations in the lithographic processes
Photolithography
Photolithography is a process used in microfabrication to selectively remove parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical "photoresist", or simply "resist," on the substrate...
used to manufacture the chips.
Traditionally, after an IC design has been converted into a physical layout
Integrated circuit layout
Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit.When...
, the timing verified
Static timing analysis
Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...
, and the polygons certified to be DRC-clean
Design rule checking
Design Rule Checking or Check is the area of Electronic Design Automation that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called Design Rules...
, the IC was ready for fabrication. The data files representing the various layers were shipped to a mask shop, which used mask-writing equipment to convert each data layer into a corresponding mask, and the masks were shipped to the fab where they were used to repeatedly manufacture the designs in silicon. In the past, the creation of the IC layout was the end of the involvement of electronic design automation
Electronic design automation
Electronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...
.
However, as Moore’s law has driven features to ever-smaller dimensions, new physical effects that could be effectively ignored in the past are now having an impact on the features that are formed on the silicon wafer. So even though the final layout may represent what is desired in silicon, the layout can still undergo dramatic alteration through several EDA tools before the masks are fabricated and shipped.
These alterations are required not to make any change in the device as designed, but to simply allow the manufacturing equipment, often purchased and optimized for making ICs one or two generations behind, to deliver the new devices. These alterations can be classed as being of two types.
The first type is distortion corrections, namely pre-compensating for distortions inherent in the manufacturing process, be it from a processing step, such as: photolithography
Photolithography
Photolithography is a process used in microfabrication to selectively remove parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical "photoresist", or simply "resist," on the substrate...
, etching, planarization, and deposition. These distortions are measured and a suitable model fitted, compensation is carried out usually using a rule or model based algorithm. When applied to printing distortions during photolithography, this distortion compensation is known as Optical Proximity Correction
Optical proximity correction
Optical proximity correction is a photolithography enhancement technique commonly used to compensate for image errors due to diffraction or process effects...
(OPC).
The second type of Reticle Enhancement involves actually improving the manufacturability or resolution of the process. Examples of this include:
| RET Technique | Manufacturability Improvement |
|---|---|
| Scattering Bars | Sub resolution assist features that improves the depth of focus of isolated features. |
| Phase-shift Mask | Etching quartz from certain areas of the mask (alt-PSM) or replacing Chrome with phase shifting Molybdenum Silicide layer (attenuated embedded PSM) to improve CD control and increase resolution |
| Double or Multiple Patterning Double patterning Multiple patterning is a class of technologies for manufacturing integrated circuits , developed for photolithography to enhance the feature density. The simplest case of multiple patterning is double patterning, where a conventional lithography process is enhanced to produce double the expected... |
Involves decomposing the design across multiple masks to allow the printing of tighter pitches. |
For each of these manufacturability improvement techniques there are certain layouts that either cannot be improved or cause issues in printing. These are classed as non-compliant layouts. These are avoided either at the design stage - using, for instance, Radically Restrictive Design Rules and/or creating addition DRC checks if appropriate. Both the lithographic compensations and manufacturability improvements are usually grouped under the heading resolution enhancement techniques (RET). Such techniques have been used since the 180nm node and have become more aggressively used as minimum feature size as dropped significantly below that of the imaging wavelength, currently limited to 193 nm.
This is closely related to, and a part of, the more general category of design for manufacturability (IC)
Design for manufacturability (IC)
Achieving high-yielding designs in the state of the art, VLSI technology has become an extremely challenging task due to the miniaturization as well as the complexity of leading-edge products...
or DFM.
After RET, the next step in an EDA flow is usually mask data preparation
Mask data preparation
Mask data preparation is the step that translates an intended set of polygons on an integrated circuit layout into a form that can be physically written by the photomask writer. Usually this involves fracturing complex polygons into simpler shapes, often rectangles and trapezoids, that can be...
.