In the automated

Electronic design automation

Electronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...

 design of integrated circuit

Integrated circuit

An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...

s, signoff (also written as sign-off) checks is the collective name given to a series of verification steps that must pass before the design can be taped out. This implies an iterative process involving incremental fixes across the board in one or more check type and retesting the design.

Check types

Signoff checks have become more complex as VLSI designs approach 32nm and 22nm process nodes because of the increased impact of previously ignored (or more crudely approximated) second order effects. There are several categories of signoff checks.

• DRC
  Design rule checking
  Design Rule Checking or Check is the area of Electronic Design Automation that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called Design Rules...
  
   - Also sometimes known as geometric verification, this involves verifying if the design can be reliably manufactured
  Semiconductor fabrication
  Semiconductor device fabrication is the process used to create the integrated circuits that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer...
  
   given current photolithography limitations. In advanced process nodes, DFM
  Design for manufacturability (IC)
  Achieving high-yielding designs in the state of the art, VLSI technology has become an extremely challenging task due to the miniaturization as well as the complexity of leading-edge products...
  
   rules are upgraded from optional (for better yield) to required.
• LVS
  Layout versus schematic
  The Layout Versus Schematic is the class of electronic design automation verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design.-Background:...
  
   - Also known as schematic verification, this is used to verify that the placement and routing of the standard cell
  Standard cell
  In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration layout is encapsulated into an...
  
  s in the design has not altered the functionality of the constructed circuit.
• Formal verification
  Formal verification
  In the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics .- Usage :Formal verification can be...
  
   - Here, the logical functionality of the post-layout
  Integrated circuit layout
  Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit.When...
  
   netlist (including any layout-driven optimization) is verified against the pre-layout, post-synthesis
  Logic synthesis
  In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...
  
   netlist
  Netlist
  The word netlist can be used in several different contexts, but perhaps the most popular is in the field of electronic design. In this context, a "netlist" describes the connectivity of an electronic design....
  
  .
• Voltage drop
  Power network design (IC)
  In integrated circuits, electrical power is distributed to the components of the chip over a network of conductors on the chip. Power network design includes the analysis and design of such networks...
  
   analysis - Also known as IR-drop analysis, this check verifies if the power grid
  Power network design (IC)
  In integrated circuits, electrical power is distributed to the components of the chip over a network of conductors on the chip. Power network design includes the analysis and design of such networks...
  
   is strong enough to ensure that the voltage representing the binary high value never dips lower than a set margin (below which the circuit will not function correctly or reliably) due to the combined switching of millions of transistors.
• Signal integrity
  Signal integrity
  Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise,...
  
   analysis - Here, noise due to crosstalk and other issues is analyzed, and its effect on circuit functionality is checked to ensure that capacitive glitches are not large enough to cross the threshold voltage
  Threshold voltage
  The threshold voltage of a MOSFET is usually defined as the gate voltage where an inversion layer forms at the interface between the insulating layer and the substrate of the transistor. The purpose of the inversion layer's forming is to allow the flow of electrons through the gate-source junction...
  
   of gates along the data path.
• Static timing analysis
  Static timing analysis
  Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...
  
   (STA) - Slowly being superseded by statistical static timing analysis
  Statistical static timing analysis
  Conventional static timing analysis has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, in recent years the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional STA...
  
   (SSTA), STA is used to verify if all the logic data paths in the design can work at the intended clock frequency, especially under the effects of on-chip variation
  Process corners
  In semiconductor manufacturing, a process corner is an example of a design-of-experiments technique that refers to a variation of fabrication parameters used in applying an integrated circuit design to a semiconductor wafer. Process corners represent the extremes of these parameter variations...
  
  . STA is run as a replacement for SPICE
  SPICE
  SPICE is a general-purpose, open source analog electronic circuit simulator.It is a powerful program that is used in integrated circuit and board-level design to check the integrity of circuit designs and to predict circuit behavior.- Introduction :Unlike board-level designs composed of discrete...
  
  , because SPICE simulation's runtime makes it infeasible for full-chip analysis modern designs.
• Electromigration
  Electromigration
  Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect is important in applications where high direct current densities are used, such as in...
  
   lifetime checks - To ensure a minimum lifetime of operation at the intended clock frequency without the circuit succumbing to electromigration
  Electromigration
  Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect is important in applications where high direct current densities are used, such as in...
  
  .

Tools

A small subset of tools are classified as "golden" or signoff-quality. Categorizing a tool as signoff-quality without vendor-bias is a matter of trial and error, since the accuracy of the tool can only be determined after the design has been fabricated. So, one of the metrics that is in use (and often touted by the tool manufacturer/vendor) is the number of successful tapeouts enabled by the tool in question. It has been argued that this metric is insufficient, ill-defined, and irrelevant for certain tools, especially tools that play only a part in the full flow.

While vendors often embellish the ease of end-to-end (typically RTL

Register transfer level

In integrated circuit design, register-transfer level is a level of abstraction used in describing the operation of a synchronous digital circuit...

 to GDS

GDSII

GDSII stream format, common acronym GDSII, is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork. It is a binary file format representing planar geometric shapes, text labels, and other information about the layout in...

 for ASIC

ASIC

ASIC may refer to:* Application-specific integrated circuit, an integrated circuit developed for a particular use, as opposed to a customised general-purpose device.* ASIC programming language, a dialect of BASIC...

s, and RTL to timing closure

Timing Closure

Timing closure is the process by which an FPGA or a VLSI design is modified to meet its timing requirements. Most of the modifications are handled by EDA tools based on directives given by a designer...

 for FPGAs) execution through their respective tool suite, most semiconductor design companies use a combination of tools from various vendors (often called "best of breed

Best of Breed

Best of Breed is the title given to the dog who has been judged the best representative specimen of its breed at a conformation show.Dogs compete in a hierarchical fashion at each show, where winners at lower levels are gradually combined to narrow the winners until the final round, where Best in...

" tools) in order to minimize correlation errors pre- and post-silicon. Since independent tool evaluation is expensive (single licenses for design tools from major vendors like Synopsys

Synopsys

Synopsys, Inc. is one of the largest companies in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit...

 and Cadence

Cadence Design Systems

Cadence Design Systems, Inc is an electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc...

 may cost tens or hundreds of thousands of dollars) and a risky proposition (if the failed evaluation is done on a production design, resulting in a time to market

Time to market

In commerce, time to market is the length of time it takes from a product being conceived until its being available for sale. TTM is important in industries where products are outmoded quickly...

 delay), it is feasible only for the largest design companies (like Intel, IBM, Freescale

Freescale Semiconductor

Freescale Semiconductor, Inc. is a producer and designer of embedded hardware, with 17 billion semiconductor chips in use around the world. The company focuses on the automotive, consumer, industrial and networking markets with its product portfolio including microprocessors, microcontrollers,...

, and TI

Texas Instruments

Texas Instruments Inc. , widely known as TI, is an American company based in Dallas, Texas, United States, which develops and commercializes semiconductor and computer technology...

). As a value add, several semiconductor foundries now provide pre-evaluated reference/recommended methodologies (sometimes referred to as "RM" flows) which includes a list of recommended tools, versions, and scripts to move data from one tool to another and automate the entire process.

This list of vendors and tools is meant to be representative and is not exhaustive:

• DRC/LVS - Mentor Calibre, Magma Quartz, Synopsys Hercules, Cadence Assura
• Voltage drop analysis - Apache Redhawk, Magma Quartz Rail
• Signal integrity analysis - Cadence CeltIC (crosstalk noise), Synopsys PrimeTime SI (crosstalk delay/noise), Extreme-DA GoldTime SI (crosstalk delay/noise)
• Static timing analysis - Synopsys PrimeTime, Magma Quartz SSTA, Cadence ETS, Extreme-DA GoldTime