Three-dimensional integrated circuit

Electronics

Electronics is the branch of science, engineering and technology that deals with electrical circuits involving active electrical components such as vacuum tubes, transistors, diodes and integrated circuits, and associated passive interconnection technologies...

, a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip

Integrated circuit

An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...

in which two or more layers of active electronic component

Electronic component

An electronic component is a basic electronic element and may be available in a discrete form having two or more electrical terminals . These are intended to be connected together, usually by soldering to a printed circuit board, in order to create an electronic circuit with a particular function...

s are integrated both vertically and horizontally into a single circuit. The semiconductor industry

Semiconductor industry

The semiconductor industry is the aggregate collection of companies engaged in the design and fabrication of semiconductor devices. It formed around 1960, once the fabrication of semiconductors became a viable business...

is pursuing this promising technology in many different forms, but it is not yet widely used; consequently, the definition is still somewhat fluid.

3D ICs vs. 3D packaging

3D packaging

Integrated circuit packaging

Integrated circuit packaging is the final stage of semiconductor device fabrication per se, followed by IC testing.Packaging in ceramic or plastic prevents physical damage and corrosion and supports the electrical contacts required to assemble the integrated circuit into a system.In the integrated...

saves space by stacking separate chips in a single package

Chip carrier

A chip carrier, also known as a chip container or chip package, is a container for a transistor or an integrated circuit. The carrier usually provides metal leads, or "pins", which are sturdy enough to electrically and mechanically connect the fragile chip to a circuit board. This connection may be...

. This packaging, known as System in Package

System in package

A system-in-a-package or system in package , also known as a Chip Stack MCM, is a number of integrated circuits enclosed in a single package or module. The SiP performs all or most of the functions of an electronic system, and are typically used inside a mobile phone, digital music player, etc...

(SiP) or Chip Stack MCM

Multi-Chip Module

A multi-chip module is a specialized electronic package where multiple integrated circuits , semiconductor dies or other discrete components are packaged onto a unifying substrate, facilitating their use as a single component...

, does not integrate the chips into a single circuit. The chips in the package communicate using off-chip signaling

Signal (electrical engineering)

In the fields of communications, signal processing, and in electrical engineering more generally, a signal is any time-varying or spatial-varying quantity....

, much as if they were mounted in separate packages on a normal circuit board

Printed circuit board

A printed circuit board, or PCB, is used to mechanically support and electrically connect electronic components using conductive pathways, tracks or signal traces etched from copper sheets laminated onto a non-conductive substrate. It is also referred to as printed wiring board or etched wiring...

.
In contrast, a 3D IC is a single chip. All components on the layers communicate using on-chip signaling, whether vertically or horizontally. A 3D IC bears the same relation to a 3D package that a SoC

System-on-a-chip

A system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...

bears to a circuit board.

Notable 3D chips

The Teraflops Research Chip

Teraflops Research Chip

The Teraflops Research Chip is a research processor containing 80 cores developed by Intel Corporation's Tera-Scale Computing Research Program. The processor was officially announced February 11, 2007 and shown working at the 2007 International Solid-State Circuits Conference...

introduced in 2007 by Intel is an experimental 80-core design with stacked memory. Due to the high demand for memory bandwidth, a traditional IO approach would consume 10 to 25W. To improve upon that, Intel designers implemented a TSV-based memory bus. Each core is connected to one memory tile in the SRAM die with a link that provides 12 GB/s bandwidth, resulting in a total bandwidth of 1 TB/s while consuming only 2.2W.

In 2004, Intel presented a 3D version of the Pentium 4

Pentium 4

Pentium 4 was a line of single-core desktop and laptop central processing units , introduced by Intel on November 20, 2000 and shipped through August 8, 2008. They had a 7th-generation x86 microarchitecture, called NetBurst, which was the company's first all-new design since the introduction of the...

CPU. The chip was manufactured with two dies using face-to-face stacking, which allowed a dense via structure. Backside TSVs are used for IO and power supply. For the 3D floorplan, designers manually arranged functional blocks in each die aiming for power reduction and performance improvement. Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspots. The 3D design provides 15% performance improvement (due to eliminated pipeline stages) and 15% power saving (due to eliminated repeaters and reduced wiring) compared to the 2D Pentium 4.

An academic implementation of a 3D processor was presented in 2008 at the University of Rochester

University of Rochester

The University of Rochester is a private, nonsectarian, research university in Rochester, New York, United States. The university grants undergraduate and graduate degrees, including doctoral and professional degrees. The university has six schools and various interdisciplinary programs.The...

by Professor Eby Friedman and his students. The chip runs at a 1.4 GHz and it was designed for optimized vertical processing between the stacked chips which gives the 3D processor abilities that the traditional one layered chip could not reach. One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in harmony without any obstacles that would interfere with a piece of information traveling from one layer to another.

Manufacturing technologies

As of 2008 there are four ways to build a 3D IC:

Monolithic – Electronic components and their connections (wiring) are built in layers on a single semiconductor wafer

Wafer (electronics)

A wafer is a thin slice of semiconductor material, such as a silicon crystal, used in the fabrication of integrated circuits and other microdevices...

, which is then diced

Wafer dicing

Wafer dicing is the process by which die are separated from a wafer of semiconductor following the processing of the wafer. The dicing process can be accomplished by scribing and breaking, by mechanical sawing or by laser cutting...

into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon via

Through-silicon via

In electronic engineering, a through-silicon via is a vertical electrical connection passing completely through a silicon wafer or die...

s. Applications of this method are currently limited because creating normal transistors requires enough heat to destroy any existing wiring. This monolithic 3D-IC technology has been researched at Stanford university under a DARPA sponsored grant.

Wafer-on-Wafer – Electronic component

Electronic component

s are built on two or more semiconductor wafers

Wafer (electronics)

A wafer is a thin slice of semiconductor material, such as a silicon crystal, used in the fabrication of integrated circuits and other microdevices...

, which are then aligned, bonded, and diced

Wafer dicing

into 3D ICs. Each wafer may be thinned before or after bonding. Vertical connections

Electrical connection

An electrical connection between discrete points allows the flow of electrons . A pair of connections is needed for a circuit.Between points with a low voltage difference, direct current can be controlled by a switch...

are either built into the wafers before bonding or else created in the stack after bonding. These “through-silicon via

Through-silicon via

In electronic engineering, a through-silicon via is a vertical electrical connection passing completely through a silicon wafer or die...

s” (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad. Wafer-on-wafer bonding can reduce yields, since if any 1 of N chips in a 3D IC are defective, the entire 3D IC will be defective. Moreover, the wafers must be the same size – but many exotic materials (e.g. III-Vs) are manufactured on much smaller wafers than CMOS logic or DRAM (typically 300mm), complicating heterogeneous integration.

Die-on-Wafer – Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dice

Die (integrated circuit)

A die in the context of integrated circuits is a small block of semiconducting material, on which a given functional circuit is fabricated.Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon or other semiconductor through processes such as...

are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional dice may be added to the stacks before dicing.

Die-on-Die – Electronic components are built on multiple dice, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding. One advantage of die-on-die is that each component die can be tested first, so that one bad die does not ruin an entire stack . Moreover, each die in the 3D IC can be binned beforehand, so that they can be mixed and matched to optimize power consumption and performance (e.g. matching multiple dice from the low power process corner for a mobile application).

Benefits

Traditional scaling of semiconductor chips also improves signal propagation speed.
However, scaling from current manufacturing and chip-design technologies has become more difficult, in part because of power-density constraints, and in part because interconnects do not become faster while transistors do 3-D integrated circuits were proposed invented to address the scaling challenge by stacking 2-D dies and connecting them in the 3rd dimension. This promises to speed up communication between layered chips, compared to planar layout. 3D ICs promise many significant benefits, including:

Footprint – More functionality fits into a small space. This extends Moore’s Law and enables a new generation of tiny but powerful devices.

Cost – Partitioning a large chip into multiple smaller dies with 3D stacking can improve the yield and reduce the fabrication cost if individual dies are tested separately.

Heterogeneous integration – Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Moreover, components with incompatible manufacturing could be combined in a single 3D IC.

Shorter interconnect – The average wire length is reduced. Common figures reported by researchers are on the order of 10-15%, but this reduction mostly applies to longer interconnect, which may affect circuit delay by a greater amount. Given that 3D wires have much higher capacitance than conventional in-die wires, circuit delay may or may not improve.

Power – Keeping a signal on-chip can reduce its power consumption by 10-100 times. Shorter wires also reduce power consumption by producing less parasitic capacitance

Parasitic capacitance

In electrical circuits, parasitic capacitance, stray capacitance or, when relevant, self-capacitance , is an unavoidable and usually unwanted capacitance that exists between the parts of an electronic component or circuit simply because of their proximity to each other...

. Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation.

Design – The vertical dimension adds a higher order of connectivity and offers new design possibilities.

Circuit security – The stacked structure complicates attempts to reverse engineer

Reverse engineering

Reverse engineering is the process of discovering the technological principles of a device, object, or system through analysis of its structure, function, and operation...

the circuitry. Sensitive circuits may also be divided among the layers in such a way as to obscure the function of each layer.

Bandwidth – 3D integration allows large numbers of vertical vias between the layers. This allows construction of wide bandwidth buses between functional blocks in different layers. A typical example would be a processor+memory 3D stack, with the cache memory stacked on top of the processor. This arrangement allows a bus much wider than the typical 128 or 256 bits between the cache and processor. Wide buses in turn alleviate the memory wall problem.

Challenges

Because this technology is new it carries new challenges, including:

Yield – Each extra manufacturing step adds a risk for defects. In order for 3D ICs to be commercially viable, defects could be repaired or tolerated, or defect density can be improved.

Heat – Heat building up within the stack must be dissipated. This is an inevitable issue as electrical proximity coorrelates with thermal proximity. Specific thermal hotspots must be more carefully managed.

Design complexity – Taking full advantage of 3D integration requires sophisticated design techniques and new CAD

Computer-aided design

Computer-aided design , also known as computer-aided design and drafting , is the use of computer technology for the process of design and design-documentation. Computer Aided Drafting describes the process of drafting with a computer...

tools.

TSV-introduced overhead – TSVs are large compared to gates and impact floorplans. At the 45nm technology node, the area footprint of a 10μm x 10μm TSV is comparable to that of about 50 gates. Furthermore, manufacturability demands landing pads and keep-out zones which further increase TSV area footprint. Depending on the technology choices, TSVs block some subset of layout resources. Via-first TSVs are manufactured before metallization, thus occupy the device layer and result in placement obstacles. Via-last TSVs are manufactured after metallization and pass through the chip. Thus, they occupy both the device and metal layers, resulting in placement and routing obstacles. While the usage of TSVs is generally expected to reduce wirelength, this depends on the number of TSVs and their characteristics. Also, the granularity of inter-die partitioning impacts wirelength. It typically decreases for moderate (blocks with 20-100 modules) and coarse (block-level partitioning) granularities, but
increases for fine (gate-level partitioning) granularities.

Testing – To achieve high overall yield and reduce costs, separate testing of independent dies is essential. However, tight integration between adjacent active layers in 3D ICs entails a significant amount of interconnect between different sections of the same circuit module that were partitioned to different dies. Aside from the massive overhead introduced by required TSVs, sections of such a module, e.g., a multiplier, cannot be independently tested by conventional techniques. This particularly applies to timing-critical paths laid out in 3D.

Lack of standards – There are few standards for TSV-based 3D-IC design, manufacturing, and packaging, although this issue is being addressed. In addition, there are many integration options being explored such as via-last, via-first, via-middle; interposers or direct bonding; etc.

Heterogeneous integration supply chain – In heterogeneously integrated systems, the delay of one part from one of the different parts suppliers delays the delivery of the whole product, and so delays the revenue for each of the 3D-IC part suppliers.

Lack of clearly defined ownership – It is unclear who should own the 3D-IC integration and packaging/assembly. It could be assembly houses like ASE or the product OEM

OEM

OEM means the original manufacturer of a component for a product, which may be resold by another company.OEM may also refer to:-Computing:* OEM font, or OEM-US, the original character set of the IBM PC, circa 1981...

Design styles

Depending on partitioning granularity, different design styles can be distinguished. Gate-level integration faces multiple challenges and currently appears less practical than block-level integration.

Gate-level integration – This style partitions standard cells between multiple dies. It promises wirelength reduction and great flexibility. However, wirelength reduction may be undermined unless modules of certain minimal size are preserved. On the other hand, its adverse effects include the massive number of necessary TSVs for interconnects. This design style requires 3D place-and-route

Place and route

Place and route is a stage in the design of printed circuit boards, integrated circuits, and field-programmable gate arrays. As implied by the name, it is composed of two steps, placement and routing. The first step, placement, involves deciding where to place all electronic components, circuitry,...

tools, which are unavailable yet. Also, partitioning a design block across multiple dies implies that it cannot be fully tested before die stacking. After die stacking (post-bond testing), a single failed die can render several good dies unusable, undermining yield. This style also amplifies the impact of process variation

Process variation (semiconductor)

Process variation is the naturally occurring variation the attributes of transistors when integrated circuits are fabricated. It becomes particularly important at smaller process nodes Process variation is the naturally occurring variation the attributes of transistors (length, widths, oxide...

, especially inter-die variation. In fact, a 3D layout may yield more poorly than the same circuit laid out in 2D, contrary to the original promise of 3D IC integration. Furthermore, this design style requires to redesign available Intellectual Property, since existing IP blocks

Semiconductor intellectual property core

In electronic design a semiconductor intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or chip layout design that is the intellectual property of one party. IP cores may be licensed to another party or can be owned and used by a single party alone...

and EDA tools do not provision for 3D integration.

Block-level integration – This style assigns entire design blocks to separate dies. Design blocks subsume most of the netlist

Netlist

The word netlist can be used in several different contexts, but perhaps the most popular is in the field of electronic design. In this context, a "netlist" describes the connectivity of an electronic design....

connectivity and are linked by a small number of global interconnects. Therefore, block-level integration promises to reduce TSV overhead. Sophisticated 3D systems combining heterogeneous dies
require distinct manufacturing processes at different technology nodes for fast and low-power random logic, several memory types, analog and RF circuits, etc. Block-level integration, which allows separate and optimized manufacturing processes, thus appears crucial for 3D integration. Furthermore, this style might facilitate the transition from current 2D design towards 3D IC design. Basically, 3D-aware tools are only needed for partitioning and thermal analysis. Separate dies will be designed using (adapted) 2D tools and 2D blocks. This is motivated by the broad availability of reliable IP blocks. It is more convenient to use available 2D IP blocks and to place the mandatory TSVs in the unoccupied space between blocks instead of redesigning IP blocks and embedding TSVs. Design-for-testability

Design For Test

Design for Test is a name for design techniques that add certain testability features to a microelectronic hardware product design. The premise of the added features is that they make it easier to develop and apply manufacturing tests for the designed hardware...

structures are a key component of IP blocks and can therefore be used to facilitate testing for 3D ICs. Also, critical paths can be mostly embedded within 2D blocks, which limits the impact of TSV and inter-die variation on manufacturing yield. Finally, modern chip design often requires last-minute engineering changes. Restricting the impact of such changes to single dies is essential to limit cost.

Simulators

IntSim is an open-source CAD tool to simulate 2D and 3D-ICs. It can be used for predicting 2D/3D chip power, die size, number of metal levels and optimal sizes of metal levels based on various technology and design parameters. Users can also study scaling trends, and use IntSim to optimize their chip designs.

3D ICs vs. 3D packaging

Notable 3D chips

Manufacturing technologies

Benefits

Challenges

Design styles

Simulators

Further reading

Potential applications

Early products

Associations

Selected press references