Verilator
Encyclopedia
Verilator is a free and open source software
tool which converts Verilog
(a hardware description language
) to a cycle accurate behavioral model in C++
or SystemC
. It is restricted to modeling the synthesizable subset of Verilog and the generated models are cycle accurate, 2-state, with synthesis (zero delay) semantics. As a consequence the models typically offer higher performance than the more widely used event driven simulators, which can process the entire Verilog language and model behavior within the clock cycle. Verilator is now used within academic research, open source projects and for commercial semiconductor development. It is part of the growing body of free EDA software.
.
and FPGA design flows and in performance and power analysis. Verilator is also a popular tool for student dissertations, for example.
architecture from OpenCores
includes a cycle accurate reference model, generated from Verilog using Verilator. A recent paper described how the regression test suite for GCC
could be run against a Verilator model of the OpenRISC 1200 as a way of detecting errors in the Verilog RTL implementation.
(DEC). It was used to convert Verilog code to C for co-simulation with a C based CPU model of the Alpha processor. During the mid-1990s Duane Galbi took over responsibility for development and the technology was adopted by other groups in DEC. In 1998 DEC released the source code.
Since 2001 the technology has been developed by Wilson Snyder and others as part of the Veripool open source project. A SystemC
mode was added and the tool rewritten from scratch in C++, leading to an increase in performance.
SystemC is supported by providing a wrapper class using SystemC ports, and with sensitivity to the clock(s), which will drive the ports of the underlying C++ model.
using MATLAB interface to C++. This is how Verilog
designs can be directly simulated from MATLAB. Using compiled C++ models with MATLAB is faster than using co-simulation interface with separate HDL simulator. There is an open-source project vmodel that compiles Verilog into MEX file
using Verilator, and provides a set of functions for model simulation from MATLAB.
Open source
The term open source describes practices in production and development that promote access to the end product's source materials. Some consider open source a philosophy, others consider it a pragmatic methodology...
tool which converts Verilog
Verilog
In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
(a hardware description language
Hardware description language
In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic...
) to a cycle accurate behavioral model in C++
C++
C++ is a statically typed, free-form, multi-paradigm, compiled, general-purpose programming language. It is regarded as an intermediate-level language, as it comprises a combination of both high-level and low-level language features. It was developed by Bjarne Stroustrup starting in 1979 at Bell...
or SystemC
SystemC
SystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...
. It is restricted to modeling the synthesizable subset of Verilog and the generated models are cycle accurate, 2-state, with synthesis (zero delay) semantics. As a consequence the models typically offer higher performance than the more widely used event driven simulators, which can process the entire Verilog language and model behavior within the clock cycle. Verilator is now used within academic research, open source projects and for commercial semiconductor development. It is part of the growing body of free EDA software.
Usage
Verilator has seen its widest adoption in the academic and open source communities. The semiconductor industry has been more cautious in its adoption of an open source tool, and has the financial wherewithal to use commercial alternatives such as Model Studio from Carbon Design Systems and VTOC from ARC InternationalARC International
ARC International plc was a developer of configurable microprocessor technology and is now owned by Synopsys. ARC developed synthesisable IP and licensed it to semiconductor companies....
.
Academic
Researchers have used Verilator to develop new co-simulation environments, as part of general ASICASIC
ASIC may refer to:* Application-specific integrated circuit, an integrated circuit developed for a particular use, as opposed to a customised general-purpose device.* ASIC programming language, a dialect of BASIC...
and FPGA design flows and in performance and power analysis. Verilator is also a popular tool for student dissertations, for example.
Open Source
Verilator is an open source tool, and has in turn been adopted by a number of other projects. The Fedora Electronic Lab http://fedoraproject.org/wiki/Features/FedoraElectronicLab has adopted Verilator as part of its open source design flow for Fedora 11. The OpenRISCOpenRISC
OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures...
architecture from OpenCores
OpenCores
OpenCores is the world's largest open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies...
includes a cycle accurate reference model, generated from Verilog using Verilator. A recent paper described how the regression test suite for GCC
GNU Compiler Collection
The GNU Compiler Collection is a compiler system produced by the GNU Project supporting various programming languages. GCC is a key component of the GNU toolchain...
could be run against a Verilator model of the OpenRISC 1200 as a way of detecting errors in the Verilog RTL implementation.
Commercial
Commercially, Philips Semiconductors (now NXP) have led the way. Their use of Verilator is becoming more widespread, for example within application notes. More recently Art of Silicon have described their use of Verilator on a farm of Linux processors as a route to faster regression testing of their commercial designs. The current maintainer of Verilator identified 27 companies and universities who had reported use of Verilator or contributed to its development, including Intel, ARM, CSR, Broadcom, Raytheon, Infineon, Imperial College London and Embecosm.History
Verilator's user manual provides a short history. The tool originated in 1994 with a team led by Paul Wasson at the Core Logic Group at Digital Equipment CorporationDigital Equipment Corporation
Digital Equipment Corporation was a major American company in the computer industry and a leading vendor of computer systems, software and peripherals from the 1960s to the 1990s...
(DEC). It was used to convert Verilog code to C for co-simulation with a C based CPU model of the Alpha processor. During the mid-1990s Duane Galbi took over responsibility for development and the technology was adopted by other groups in DEC. In 1998 DEC released the source code.
Since 2001 the technology has been developed by Wilson Snyder and others as part of the Veripool open source project. A SystemC
SystemC
SystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...
mode was added and the tool rewritten from scratch in C++, leading to an increase in performance.
Technology and key features
Verilator converts synthesizable Verilog to C++ or SystemC. It can handle all versions of Verilog and also some SystemVerilog and Sugar/PSL assertions. The approach is closer to synthesis than event driven simulation. The entire design is flattened (that is all modules are expanded, to create one module). Static analysis is used to eliminate wires and schedule all processes at model generation time. Since this is a cycle accurate model, all intra-cycle delays are ignored. A C++ class is generated with a function which will take 2-state values on input ports and advance them to values on output ports at the next clock edge.SystemC is supported by providing a wrapper class using SystemC ports, and with sensitivity to the clock(s), which will drive the ports of the underlying C++ model.
Using with MATLAB
Verilator converts synthesizable Verilog to C++, while C++ library could be compiled into MEX fileMEX file
MEX stands for MATLAB Executable. A MEX file provides an interfacebetween MATLAB and subroutines written in C, C++ or Fortran.When compiled, MEX files are dynamically loaded and allow non-MATLAB code to be invoked from within...
using MATLAB interface to C++. This is how Verilog
Verilog
In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
designs can be directly simulated from MATLAB. Using compiled C++ models with MATLAB is faster than using co-simulation interface with separate HDL simulator. There is an open-source project vmodel that compiles Verilog into MEX file
MEX file
MEX stands for MATLAB Executable. A MEX file provides an interfacebetween MATLAB and subroutines written in C, C++ or Fortran.When compiled, MEX files are dynamically loaded and allow non-MATLAB code to be invoked from within...
using Verilator, and provides a set of functions for model simulation from MATLAB.
See also
- Comparison of Free EDA software
- List of Verilog Simulators
- OpenCoresOpenCoresOpenCores is the world's largest open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies...
- OpenRISCOpenRISCOpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures...
- VerilogVerilogIn the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
External links
- Carbon Design Systems home page
- Verilator home page
- vmodel home page