Wafer testing
Encyclopedia
Wafer testing is a step performed during semiconductor device fabrication. During this step, performed before a wafer is sent to die preparation
, all individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns to them. The wafer testing is performed by a piece of test equipment called a wafer prober. The process of wafer testing can be referred to in several ways: Wafer Sort (WS), Wafer Final Test (WFT), Electronic Die Sort (EDS) and Circuit Probe (CP) are probably the most common.
are held in place whilst the wafer, vacuum-mounted on a wafer chuck, is moved into electrical contact. When a die (or array of dice) have been electrically tested the prober moves the wafer to the next die (or array) and the next test can start. The wafer prober is usually responsible for loading and unloading the wafers from their carrier (or cassette) and is equipped with automatic pattern recognition optics capable of aligning the wafer with sufficient accuracy to ensure accurate registration between the contact pad
s on the wafer and the tips of the probes.
For today’s multi-die packages such as stacked chip-scale package (SCSP) or System in Package (SiP) – the development of non-contact (RF) probes for identification of known tested die (KTD) and known good die (KGD) are critical to increasing overall system yield.
The wafer prober also exercises any test circuitry on the wafer scribe lines.
Some companies get most of their information about device performance from these scribe line test structures.
When all test patterns pass for a specific die, its position is remembered for later use during IC packaging
. Sometimes a die has internal spare resources available for repairing (i.e. flash memory IC); if it does not pass some test patterns these spare resources can be used. If redundancy of failed die is not possible the die is considered faulty and is discarded. Non-passing circuits are typically marked with a small dot of ink in the middle of the die, or the information of passing/non-passing is stored in a file, named a wafermap. This map categorizes the passing and non-passing dies by making use of bins. A bin is then defined as a good or bad die. This wafermap is then sent to the die attachment
process which then only picks up the passing circuits by selecting the bin number of good dies. The process where no ink dot is used to mark the bad dies is named substrate mapping
. When ink dots are used, vision systems on subsequent die handling equipment can disqualify the die by recognizing the ink dot.
In some very specific cases, a die that passes some but not all test patterns can still be used as a product, typically with limited functionality. The most common example of this is a microprocessor for which only one part of the on-die cache
memory is functional. In this case, the processor can sometimes still be sold as a lower cost part with a smaller amount of memory and thus lower performance. Additionally when bad dies have been identified, the die from the bad bin can be used by production personnel for assembly line setup.
The contents of all test patterns and the sequence by which they are applied to an integrated circuit are called the test program.
After IC packaging, a packaged chip will be tested again during the IC testing phase, usually with the same or very similar test patterns. For this reason, one might think that wafer testing is an unnecessary, redundant step. In reality this is not usually the case, since the removal of defective dies saves the considerable cost of packaging faulty devices. However, when the production yield is so high that wafer testing is more expensive than the packaging cost of defect devices, the wafer testing step can be skipped altogether and dies will undergo blind assembly.
Die preparation
Die preparation is a step of semiconductor device fabrication during which a wafer is prepared for IC packaging and IC testing. The process of die preparation typically consists of 2 steps: wafer mounting and wafer dicing.-Wafer mounting:...
, all individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns to them. The wafer testing is performed by a piece of test equipment called a wafer prober. The process of wafer testing can be referred to in several ways: Wafer Sort (WS), Wafer Final Test (WFT), Electronic Die Sort (EDS) and Circuit Probe (CP) are probably the most common.
Wafer prober
A wafer prober is a machine used to test integrated circuits. For electrical testing a set of microscopic contacts or probes called a probe cardProbe card
A probe card is an interface between an electronic test system and a semiconductor wafer. Its purpose is to provide an electrical path between the test system and the circuits on the wafer, thereby permitting the testing and validation of the circuits at the wafer level, usually before they are...
are held in place whilst the wafer, vacuum-mounted on a wafer chuck, is moved into electrical contact. When a die (or array of dice) have been electrically tested the prober moves the wafer to the next die (or array) and the next test can start. The wafer prober is usually responsible for loading and unloading the wafers from their carrier (or cassette) and is equipped with automatic pattern recognition optics capable of aligning the wafer with sufficient accuracy to ensure accurate registration between the contact pad
Contact pad
Contact pads are designated surface areas of a printed circuit board or die of an integrated circuit. Possibilities to contact to pads include soldering, wirebonding, Flip chip mounting, or probe needles....
s on the wafer and the tips of the probes.
For today’s multi-die packages such as stacked chip-scale package (SCSP) or System in Package (SiP) – the development of non-contact (RF) probes for identification of known tested die (KTD) and known good die (KGD) are critical to increasing overall system yield.
The wafer prober also exercises any test circuitry on the wafer scribe lines.
Some companies get most of their information about device performance from these scribe line test structures.
When all test patterns pass for a specific die, its position is remembered for later use during IC packaging
Integrated circuit packaging
Integrated circuit packaging is the final stage of semiconductor device fabrication per se, followed by IC testing.Packaging in ceramic or plastic prevents physical damage and corrosion and supports the electrical contacts required to assemble the integrated circuit into a system.In the integrated...
. Sometimes a die has internal spare resources available for repairing (i.e. flash memory IC); if it does not pass some test patterns these spare resources can be used. If redundancy of failed die is not possible the die is considered faulty and is discarded. Non-passing circuits are typically marked with a small dot of ink in the middle of the die, or the information of passing/non-passing is stored in a file, named a wafermap. This map categorizes the passing and non-passing dies by making use of bins. A bin is then defined as a good or bad die. This wafermap is then sent to the die attachment
Die attachment
Die attachment is the step during the integrated circuit packaging phase of semiconductor device fabrication during which a die is mounted and fixed to the package or support structure....
process which then only picks up the passing circuits by selecting the bin number of good dies. The process where no ink dot is used to mark the bad dies is named substrate mapping
Substrate mapping
Substrate mapping, also known as 'wafer mapping' is a process in which the performance of semiconductor devices on a substrate is represented by a map showing the performance as a colour-coded grid...
. When ink dots are used, vision systems on subsequent die handling equipment can disqualify the die by recognizing the ink dot.
In some very specific cases, a die that passes some but not all test patterns can still be used as a product, typically with limited functionality. The most common example of this is a microprocessor for which only one part of the on-die cache
CPU cache
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
memory is functional. In this case, the processor can sometimes still be sold as a lower cost part with a smaller amount of memory and thus lower performance. Additionally when bad dies have been identified, the die from the bad bin can be used by production personnel for assembly line setup.
The contents of all test patterns and the sequence by which they are applied to an integrated circuit are called the test program.
After IC packaging, a packaged chip will be tested again during the IC testing phase, usually with the same or very similar test patterns. For this reason, one might think that wafer testing is an unnecessary, redundant step. In reality this is not usually the case, since the removal of defective dies saves the considerable cost of packaging faulty devices. However, when the production yield is so high that wafer testing is more expensive than the packaging cost of defect devices, the wafer testing step can be skipped altogether and dies will undergo blind assembly.
See also
- Wafer prober
- Non-contact wafer testingNon-contact wafer testingWafer testing is a normal step in semiconductor device fabrication, used to detect defects in integrated circuits before they are assembled during the IC packaging step.- Traditional wafer testing :...
- Wafer bondingWafer bondingWafer bonding is a packaging technology on wafer-level for the fabrication of microelectromechanical systems , nanoelectromechanical systems , microelectronics and optoelectronics, ensuring a mechanically stable and hermetically sealed encapsulation...
- Bond characterizationBond characterizationThe wafer bond characterization is based on different methods and tests. Considered a high importance of the wafer are the successful bonded wafers without flaws. Those flaws can be caused by void formation in the interface due to unevenness or impurities...