HLV
Encyclopedia
High-level verification (HLV), or electronic system level
verification, is the task to verify ESL designs at high abstraction level. i.e. it is the task to verify a model that represents hardware above register transfer level
abstract level. For HLS High-level synthesis
( or c synthesis ), HLV is to HLS
as functional verification
is to logic synthesis
.
Electronic digital hardware design has evolved from low level abstraction at gate level to register transfer level
(RTL), the abstraction level above RTL is commonly called high-level, ESL, or behavioral/algorithmic level.
In High-level synthesis
, behavioral/algorithmic designs in ANSI C/C++/SystemC code is synthesized to RTL, which is then synthesized into gate level through logic synthesis
. Functional verification
is the task to make sure a design at RTL or gate level conforms to a specification. As logic synthesis matures, most functional verification is done at the higher abstraction, i.e. at RTL level, the correctness of logic synthesis tool in the translating process from RTL description to gate netlist is a less concern today.
High-level synthesis is still an emerging technology, so High-level verification today has two important areas under development:
1) to validate HLS is correct in the translation process, i.e. to validate the design before and after HLS are equivalent, typically through formal methods
2) to verify a design in ANSI C/C++/SystemC code is conforming to a specification, typically through simulation
.
Simulation Solution: Intelligent stimulus generation, code and functional coverage, temporal assertion checker
Electronic system level
Electronic system level design and verification is an emerging electronic design methodology that focuses on the higher abstraction level concerns first and foremost. The term Electronic System Level or ESL Design was first defined by Gartner Dataquest, a EDA-industry-analysis firm, on February...
verification, is the task to verify ESL designs at high abstraction level. i.e. it is the task to verify a model that represents hardware above register transfer level
Register transfer level
In integrated circuit design, register-transfer level is a level of abstraction used in describing the operation of a synchronous digital circuit...
abstract level. For HLS High-level synthesis
High-level synthesis
High-level synthesis , sometimes referred to as C synthesis, electronic system level synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates hardware that implements that behavior. The...
( or c synthesis ), HLV is to HLS
HLS
HLS has a number of meanings:*Harvard Law School*High-level synthesis*Historisches Lexikon der Schweiz, a Swiss encyclopedia.*Hue, Saturation, Lightness color space...
as functional verification
Functional verification
Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, and takes the...
is to logic synthesis
Logic synthesis
In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...
.
Electronic digital hardware design has evolved from low level abstraction at gate level to register transfer level
Register transfer level
In integrated circuit design, register-transfer level is a level of abstraction used in describing the operation of a synchronous digital circuit...
(RTL), the abstraction level above RTL is commonly called high-level, ESL, or behavioral/algorithmic level.
In High-level synthesis
High-level synthesis
High-level synthesis , sometimes referred to as C synthesis, electronic system level synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates hardware that implements that behavior. The...
, behavioral/algorithmic designs in ANSI C/C++/SystemC code is synthesized to RTL, which is then synthesized into gate level through logic synthesis
Logic synthesis
In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...
. Functional verification
Functional verification
Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, and takes the...
is the task to make sure a design at RTL or gate level conforms to a specification. As logic synthesis matures, most functional verification is done at the higher abstraction, i.e. at RTL level, the correctness of logic synthesis tool in the translating process from RTL description to gate netlist is a less concern today.
High-level synthesis is still an emerging technology, so High-level verification today has two important areas under development:
1) to validate HLS is correct in the translation process, i.e. to validate the design before and after HLS are equivalent, typically through formal methods
Formal methods
In computer science and software engineering, formal methods are a particular kind of mathematically-based techniques for the specification, development and verification of software and hardware systems...
2) to verify a design in ANSI C/C++/SystemC code is conforming to a specification, typically through simulation
Simulation
Simulation is the imitation of some real thing available, state of affairs, or process. The act of simulating something generally entails representing certain key characteristics or behaviours of a selected physical or abstract system....
.
Product Areas
Formal Solution: Verify high level models against RTL designsSimulation Solution: Intelligent stimulus generation, code and functional coverage, temporal assertion checker
See also
- Electronic system levelElectronic system levelElectronic system level design and verification is an emerging electronic design methodology that focuses on the higher abstraction level concerns first and foremost. The term Electronic System Level or ESL Design was first defined by Gartner Dataquest, a EDA-industry-analysis firm, on February...
- SystemCSystemCSystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...
- SystemVerilogSystemVerilogIn the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...
- Property Specification LanguageProperty Specification LanguageProperty Specification Language is a language developed by Accellera for specifying properties or assertions about hardware designs. The properties can then be simulated or formally verified. Since September 2004 the standardization on the language has been done in IEEE 1850 working group...
- Transaction-level modelingTransaction-level modelingTransaction-level modeling is a high-level approach to modeling digital systems where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. Communication mechanisms such as busesor FIFOs are modeled as...
- Functional verificationFunctional verificationFunctional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, and takes the...
- Formal verificationFormal verificationIn the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics .- Usage :Formal verification can be...