Aldec
Encyclopedia
Overview
Aldec provides software and hardware used in creation and verification of digital designs targeting FPGA and ASICASIC
ASIC may refer to:* Application-specific integrated circuit, an integrated circuit developed for a particular use, as opposed to a customised general-purpose device.* ASIC programming language, a dialect of BASIC...
technologies. Headquartered in Henderson, Nevada
Henderson, Nevada
-Demographics:According to the 2000 census, there were 175,381 people, 66,331 households, and 47,095 families residing in the city. The population density was 2,200.8 people per square mile . There were 71,149 housing units at an average density of 892.8 per square mile...
, Aldec also has offices/development centers in Europe(UK), Japan, Israel, India, China, Taiwan, Poland and Ukraine.
As a member of Accellera
Accellera
Accellera is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation and IC design and manufacturing. It is less constrained than the IEEE and is therefore the starting place for many standards. Once...
and IEEE Standards Association
IEEE Standards Association
The Institute of Electrical and Electronics Engineers Standards Association is an organization within IEEE that develops global standards in a broad range of industries, including: power and energy, biomedical and health care, information technology, telecommunication, transportation,...
Aldec actively participates in the process of developing new standards and updating existing standards (e.g. VHDL, SystemVerilog
SystemVerilog
In the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...
).
Aldec provides HDL simulation engine for other EDA tools (e.g. Altium Designer
Altium Designer
Altium Designer is an EDA software package for printed circuit board, FPGA and embedded software design, and associated library and release management automation...
) and bundles special version of its tools with FPGA
Field-programmable gate array
A field-programmable gate array is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable"...
vendors software (e.g. Lattice
Lattice Semiconductor
Lattice Semiconductor Corporation is a United States based manufacturer of high-performance programmable logic devices . Founded in 1983, the company employs about 700 people and has annual revenues of around $300 million, with Darin Billerbeck as the chief executive officer...
).
Software
- Active-HDL - FPGA development environment built around common kernel HDL simulator. Supports text-based and graphical design entry and debugging tools, allows mixed-language simulation (VHDL/Verilog/EDIF/SystemC/SystemVerilog) and provides unified interface to various synthesis and implementation tools. Also supports assertion based verification with Open Vera, PSL, or Systemverilog Assertion statements. Special versions of the software that support just one FPGA vendor are available, e.g. Active-HDL Lattice Edition. Only available on MS Windows platform.
- Riviera-PRO - high-end HDL simulator targeting ASIC and large FPGA designs. Riviera extends Active-HDL's simulation features with support for advanced verification methodologies such as linting, functional coverage, OVMOpen Verification MethodologyThe Open Verification Methodology is a documented methodology with a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008, and regular updates have expanded its functionality. The latest version is OVM...
and UVMUniversal Verification MethodologyThe Universal Verification Methodology is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM which was, to a large part, based on the eRM for the e Verification Language developed by Verisity Design in 2001...
, hardware acceleration, and prototyping. Riviera-PRO is a new generation of the tool known as Riviera-Classic and is available in 32-bit and 64-bit on MS Windows and Linux.
- ALINT - dedicated design rule checker/linting tool. ALINT is able to conduct extensive textual analysis of individual Verilog and VHDL sources and advanced checks of the entire design hierarchy. Multiple sets of highly configurable, predefined rules are available and new, custom rules can be created using provided API. Built-in Phase-Based Linting methodology allows faster, more efficient checking of rules.
- Server Farm Manager (SFM) - web-based, regression testing automation solution that automates the scheduling, execution, result analysis, and reporting of tens-to-thousands of parallel simulations from one control point. Platform independent.
- IP Products - a set of general-purpose Intellectual Property blocks created by Aldec and its partners, validated in Active-HDL and Riviera environments.
Hardware
- HES - solution allowing acceleration of HDL simulation (10x to 50x verification time reduction), emulation of the entire design (e.g. prototyping of an ASIC using FPGAs) and hardware/software co-simulation (useful in Embedded SystemEmbedded systemAn embedded system is a computer system designed for specific control functions within a larger system. often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts. By contrast, a general-purpose computer, such as a personal...
development).
- Actel RTAX/RTSX Prototyping - the efficient way of prototyping designs with radiation hardened FPGA by using footprint-compatible prototyping boards with flash-based, reprogrammable chips on top. The solution includes optional software for netlist translation.
- DO-254 Compliance Tool Set (CTS) - It is a complete verification solution that can assure the FPGA on your system to be DO-254/ED80 compliant. The CTS gives the user the ability to perform an advanced way of In-Hardware Simulation instead of the traditional Hardware Testing. As test vectors for the In-Hardware Simulation, you can reuse the same testbench with 100% Code Coverage results captured from RTL simulation. By reusing the same testbench, the Hardware Verification can easily achieve requirements traceability. You can perform the In-Hardware Simulation at speed at the target device. The CTS also allows easy comparison and debugging of the In-Hardware Simulation and HDL Simulation results via waveform format.
Education
Aldec provides fully functional, heavily discounted versions of its software for educational institutions worldwide (Kumaon Engineering CollegeKumaon Engineering College
The BIPIN CHANDRA TRIPATHI KUMAON ENGINEERING COLLEGE is an autonomous engineering and technology institute in the Ranikhet district in state of Uttarakhand, India. The college was established by the then Govt. of Uttar Pradesh in 1986 for imparting engineering education and promoting...
, National Technology University).
Aldec also offers a special Student-Edition of Active-HDL, downloadable from Aldec's website. The Student-Edition has limited design capacity and some reduction of program functionality, but supports both design languages (Verilog/VHDL.)
The company also supports local education - in 1999 it contributed to the establishment of the "Aldec Digital Design Laboratory" at the UNLV.
Aldec software is packaged with several electronic design related books (e.g. "Digital Design: Principles and Practices", "CONTEMPORARY LOGIC DESIGN").
History
- Aldec was founded in 1984 by Dr. Stanley M. Hyduke.
- In 1985 the company released its first product: MS DOS-based gate-level simulator SUSIE. For the next couple of years several versions of the product were used as companion simulators for popular schematic entry tools such as OrCADOrCADOrCAD is a proprietary software tool suite used primarily for electronic design automation. The software is used mainly to create electronic prints for manufacturing of printed circuit boards, by electronic design engineers and electronic technicians to manufacture electronic schematics.The name...
.
- Sensing growing popularity of Microsoft Windows, ALDEC ported its simulator to this platform and added schematic entry and design management tool. The new software suite was released in 1992 as Active-CAD (some low-end versions of the suite were for some time sold under Susie-CAD brand). One of the distinguishing features of Active-CAD was the ability of instantaneous transfer of schematic changes to the simulator, allowing quick verification of the behavior of the modified circuit.
- In 1996 Aldec signed agreement with XilinxXilinxXilinx, Inc. is a supplier of programmable logic devices. It is known for inventing the field programmable gate array and as the first semiconductor company with a fabless manufacturing model....
that allowed distribution of Xilinx-only version of Active-CAD under the Foundation name.
- While VHDL and VerilogVerilogIn the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
were supported by Active-CAD in the form of schematic macros, the release of Active-VHDL in 1997 marked the shift from netlist-based design to HDL-based design. After adding Verilog support, Active-VHDL was renamed to Active-HDL and is still available (as of 2007).
- In 2000 ALDEC released high-performance HDL simulator working not only on WindowsMicrosoft WindowsMicrosoft Windows is a series of operating systems produced by Microsoft.Microsoft introduced an operating environment named Windows on November 20, 1985 as an add-on to MS-DOS in response to the growing interest in graphical user interfaces . Microsoft Windows came to dominate the world's personal...
, but also on Solaris and LinuxLinuxLinux is a Unix-like computer operating system assembled under the model of free and open source software development and distribution. The defining component of any Linux system is the Linux kernel, an operating system kernel first released October 5, 1991 by Linus Torvalds...
platforms.
- In 2001 ALDEC added hardware to its product line: HES Platform that allows hardware acceleration of HDL simulation and incremental prototyping of hardware.
- Year 2003 marks the release of Riviera supporting assertion based verification (OpenVeraOpenVeraOpenVera is a dead Hardware Verification Language developed, and managed by Synopsys.OpenVera is an interoperable, open hardware verification language for testbench creation. The OpenVera language was used as the basis for the advanced verification features in the IEEE Std...
, PSLProperty Specification LanguageProperty Specification Language is a language developed by Accellera for specifying properties or assertions about hardware designs. The properties can then be simulated or formally verified. Since September 2004 the standardization on the language has been done in IEEE 1850 working group...
and SystemVerilogSystemVerilogIn the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...
can be used to write properties, assertions and coverage.)
- Support for SystemCSystemCSystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...
and non-assertion part of SystemVerilogSystemVerilogIn the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...
was added in 2004. Interfaces to MATLABMATLABMATLAB is a numerical computing environment and fourth-generation programming language. Developed by MathWorks, MATLAB allows matrix manipulations, plotting of functions and data, implementation of algorithms, creation of user interfaces, and interfacing with programs written in other languages,...
and SimulinkSimulinkSimulink, developed by MathWorks, is a commercial tool for modeling, simulating and analyzing multidomain dynamic systems. Its primary interface is a graphical block diagramming tool and a customizable set of block libraries. It offers tight integration with the rest of the MATLAB environment and...
appeared in Aldec tools for the first time in 2005.
- In 2006 Riviera was the first simulator supporting Open IP Encryption Initiative by SynplicitySynplicitySynplicity Inc. was a supplier of software solutions for design of programmable logic devices used for communications, military/aerospace, consumer, semiconductor, computer and other electronic systems. Synplicity’s tools provided logic synthesis, physical synthesis, and verification functions for...
.
- Stimulated by requests from Verilog users, ALDEC released in 2007 an advanced, user-configurable lint tool implementing rules created by STARC - Japanese consortium of major silicon vendors.
Trivia
- Student Edition of Active-HDL was the first HDL simulator to be sold at Walmart.
- The name of the first Aldec product - SUSIE - is an acronym for Standard Universal Simulator for Improved Engineering.