Computational lithography
Encyclopedia
Computational lithography (also known as computational scaling) is the set of mathematical and algorithmic approaches designed to improve the resolution attainable through photolithography
. Computational lithography has come to the forefront of photolithography
in 2008 as the semiconductor industry
grappled with the challenges associated with the transition to 22 nanometer
CMOS
process technology and beyond.
has been a driving force behind Moore's Law
. Resolution improvements enable printing of smaller geometries on an integrated circuit
. The minimum feature size that a projection system typically used in photolithography
can print is given approximately by:
where
is the minimum feature size (also called the critical dimension).
is the wavelength
of light used.
is the numerical aperture
of the lens as seen from the wafer.
(commonly called k1 factor) is a coefficient that encapsulates process-related factors.
Historically, resolution enhancements in photolithography
have been achieved through the progression of stepper
illumination sources to smaller and smaller wavelengths — from "g-line" (436 nm) and "i-line" (365 nm) sources based on mercury lamps, to the current systems based on deep ultraviolet excimer laser
s sources at 193 nm. However the progression to yet finer wavelength sources has been stalled by the intractable problems associated with extreme ultraviolet lithography
and x-ray lithography
, forcing semiconductor manufacturers to extend the current 193 nm optical lithography systems until some form of next-generation lithography
proves viable (although 157 nm steppers have also been marketed, they have proven cost-prohibitive at $50M each). Efforts to improve resolution by increasing the numerical aperture have led to the use of immersion lithography
. As further improvements in resolution through wavelength reduction or increases in numerical aperture have become either technically challenging or economically unfeasible, much attention has been paid to reducing the k1-factor. The k1 factor can be reduced through process improvements, such as phase-shift photomasks. These techniques have enabled photolithography
at the 32 nanometer
CMOS process technology node using a wavelength of 193nm (deep ultraviolet). However, with the ITRS roadmap
calling for the 22 nanometer
node to be in use by 2011, photolithography researchers have had to develop an additional suite of improvements to make 22 nm technology manufacturable. While the increase in mathematical modeling has been underway for some time, the degree and expense of those calculations has justified the use of a new term to cover the changing landscape: computational lithography.
, Rick Dill at IBM and Andy Neureuther at Univ Berkeley from the early 1980s. These tools were limited to lithography process optimization as the algorithms were limited to a few square micrometres of resist. Commercial full-chip optical proximity correction, using model forms, was first implemented by TMA (now a subsidiary of Synopsys
) around 1997. Since then the market and complexity has grown significantly. With the move to sub-wavelength lithography at the 180nm and 130nm nodes, RET techniques such as Assist features, Phase Shift Masks started to be used together with OPC. For the transition from 65nm to 45nm nodes customers were worrying that not only that design rules were insufficient to guarantee printing without yield limiting hotspots, but also that tape-out time may need thousands of CPUs or weeks of run time. This predicted exponential increase in computational complexity for mask synthesis on moving to the 45nm process node spawned a significant venture capital investment in Design for Manufacturing
start-up companies. A number of startup companies promoting their own disruptive solutions to this problem, started to appear, techniques from custom hardware acceleration to radical new algorithms such as Inverse Lithography were touted to resolve the forthcoming bottlenecks. Despite all this activity, incumbent OPC suppliers were able to adapt and keep their major customers, with RET and OPC being used together as for previous nodes, but now on more layers and with larger data files, and turn around time concerns were met by new algorithms and improvements in multi-core commodity processors. The term computational lithography was first used by Brion Technology (now a subsidiary of ASML
) in 2005 to promote their hardware accelerated full chip lithography simulation platform. Since then the term has been used by the industry to describe full chip mask synthesis solutions. As 45 nm goes into full production and EUV lithography introduction is delayed, 32 nm and 22 nm are expected to run on existing 193 nm scanners technology. Now, not only are throughput and capabilities concerns resurfacing, but also new computational lithography techniques such as Source Mask Optimization (SMO) is seen as a way to squeeze better resolution specific to a given design. Today, all the major Mask Synthesis vendors have settled on the term "Computational Lithography" to describe and promote the set of Mask Synthesis technologies required for 22 nm.
(RET), Optical Proximity Correction
(OPC), Source Mask Optimization (SMO), etc. The techniques vary in terms of their technical feasibility and engineering sensible-ness, resulting in the adoption of some and the continual R&D of others.
, first used in the 90 nanometer
generation, using the mathematics of diffraction optics to specify multi-layer phase-shift photomasks that use interference patterns in the photomask that enhance resolution on the printed wafer surface.
uses computational methods to counteract the effects of diffraction-related blurring and under-exposure by modifying on-mask geometries with means such as:
OPC can be broadly divided into rule-based and model-based.
Inverse lithography technology, which treats the OPC as an inverse imaging problem, is also a useful technique because it can provide unintuitive mask patterns.
, the largest manufacturer of photolithography systems, markets a rack-mounted hardware accelerator dedicated for use in making computational lithographic calculations — a mask-making shop can purchase a large number of their systems to run in parallel. Others have claimed significant acceleration using off-the-shelf graphics cards used for computer gaming.
Photolithography
Photolithography is a process used in microfabrication to selectively remove parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical "photoresist", or simply "resist," on the substrate...
. Computational lithography has come to the forefront of photolithography
Photolithography
Photolithography is a process used in microfabrication to selectively remove parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical "photoresist", or simply "resist," on the substrate...
in 2008 as the semiconductor industry
Semiconductor industry
The semiconductor industry is the aggregate collection of companies engaged in the design and fabrication of semiconductor devices. It formed around 1960, once the fabrication of semiconductors became a viable business...
grappled with the challenges associated with the transition to 22 nanometer
22 nanometer
The 22 nanometer node is the CMOS process step following 32 nm. It was introduced by semiconductor companies in 2011. The typical half-pitch for a memory cell is around 22 nm...
CMOS
CMOS
Complementary metal–oxide–semiconductor is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits...
process technology and beyond.
Context: industry forced to extend 193nm deep UV photolithography
The periodic enhancement in the resolution achieved through photolithographyPhotolithography
Photolithography is a process used in microfabrication to selectively remove parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical "photoresist", or simply "resist," on the substrate...
has been a driving force behind Moore's Law
Moore's Law
Moore's law describes a long-term trend in the history of computing hardware: the number of transistors that can be placed inexpensively on an integrated circuit doubles approximately every two years....
. Resolution improvements enable printing of smaller geometries on an integrated circuit
Integrated circuit
An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...
. The minimum feature size that a projection system typically used in photolithography
Photolithography
Photolithography is a process used in microfabrication to selectively remove parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical "photoresist", or simply "resist," on the substrate...
can print is given approximately by:
where
is the minimum feature size (also called the critical dimension). is the wavelengthWavelength
In physics, the wavelength of a sinusoidal wave is the spatial period of the wave—the distance over which the wave's shape repeats.It is usually determined by considering the distance between consecutive corresponding points of the same phase, such as crests, troughs, or zero crossings, and is a...
of light used.
is the numerical apertureNumerical aperture
In optics, the numerical aperture of an optical system is a dimensionless number that characterizes the range of angles over which the system can accept or emit light. By incorporating index of refraction in its definition, NA has the property that it is constant for a beam as it goes from one...
of the lens as seen from the wafer.
(commonly called k1 factor) is a coefficient that encapsulates process-related factors.Historically, resolution enhancements in photolithography
Photolithography
Photolithography is a process used in microfabrication to selectively remove parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical "photoresist", or simply "resist," on the substrate...
have been achieved through the progression of stepper
Stepper
A stepper is a device used in the manufacture of integrated circuits that is similar in operation to a slide projector or a photographic enlarger. Steppers are an essential part of the complex process, called photolithography, that creates millions of microscopic circuit elements on the surface of...
illumination sources to smaller and smaller wavelengths — from "g-line" (436 nm) and "i-line" (365 nm) sources based on mercury lamps, to the current systems based on deep ultraviolet excimer laser
Excimer laser
An excimer laser is a form of ultraviolet laser which is commonly used in the production of microelectronic devices , eye surgery, and micromachining....
s sources at 193 nm. However the progression to yet finer wavelength sources has been stalled by the intractable problems associated with extreme ultraviolet lithography
Extreme ultraviolet lithography
Extreme ultraviolet lithography is a next-generation lithography technology using an extreme ultraviolet wavelength, currently expected to be 13.5 nm.-EUVL light source:...
and x-ray lithography
X-ray lithography
300px|thumbX-ray lithography, is a process used in electronic industry to selectively remove parts of a thin film. It uses X-rays to transfer a geometric pattern from a mask to a light-sensitive chemical photoresist, or simply "resist," on the substrate...
, forcing semiconductor manufacturers to extend the current 193 nm optical lithography systems until some form of next-generation lithography
Next-generation lithography
Next-generation lithography is a term used in integrated circuit manufacturing to describe the lithography technologies slated to replace photolithography. As of 2009 the most advanced form of photolithography is immersion lithography, in which water is used as an immersion medium for the final...
proves viable (although 157 nm steppers have also been marketed, they have proven cost-prohibitive at $50M each). Efforts to improve resolution by increasing the numerical aperture have led to the use of immersion lithography
Immersion lithography
Immersion lithography is a photolithography resolution enhancement technique for manufacturing integrated circuits that replaces the usual air gap between the final lens and the wafer surface with a liquid medium that has a refractive index greater than one. The resolution is increased by a factor...
. As further improvements in resolution through wavelength reduction or increases in numerical aperture have become either technically challenging or economically unfeasible, much attention has been paid to reducing the k1-factor. The k1 factor can be reduced through process improvements, such as phase-shift photomasks. These techniques have enabled photolithography
Photolithography
Photolithography is a process used in microfabrication to selectively remove parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical "photoresist", or simply "resist," on the substrate...
at the 32 nanometer
32 nanometer
The 32 nm process is the step following the 45 nanometer process in CMOS semiconductor device fabrication. 32 nanometer refers to the average half-pitch of a memory cell at this technology level...
CMOS process technology node using a wavelength of 193nm (deep ultraviolet). However, with the ITRS roadmap
International Technology Roadmap for Semiconductors
The International Technology Roadmap for Semiconductors is a set of documents produced by a group of semiconductor industry experts. These experts are representative of the sponsoring organisations which include the Semiconductor Industry Associations of the US, Europe, Japan, South Korea and...
calling for the 22 nanometer
22 nanometer
The 22 nanometer node is the CMOS process step following 32 nm. It was introduced by semiconductor companies in 2011. The typical half-pitch for a memory cell is around 22 nm...
node to be in use by 2011, photolithography researchers have had to develop an additional suite of improvements to make 22 nm technology manufacturable. While the increase in mathematical modeling has been underway for some time, the degree and expense of those calculations has justified the use of a new term to cover the changing landscape: computational lithography.
A short history of computational lithography
Computational Lithography means the use of computers to simulate printing of micro-lithography structures. Pioneering work was done by Chris Mack at NSA in developing PROLITHPROLITH
PROLITH is a computer simulator modeling the optical and chemical aspects of photolithography. Chris Mack started developing PROLITH after he began working in the field of photolithography at the NSA in 1983.PROLITH was first developed on an IBM PC...
, Rick Dill at IBM and Andy Neureuther at Univ Berkeley from the early 1980s. These tools were limited to lithography process optimization as the algorithms were limited to a few square micrometres of resist. Commercial full-chip optical proximity correction, using model forms, was first implemented by TMA (now a subsidiary of Synopsys
Synopsys
Synopsys, Inc. is one of the largest companies in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit...
) around 1997. Since then the market and complexity has grown significantly. With the move to sub-wavelength lithography at the 180nm and 130nm nodes, RET techniques such as Assist features, Phase Shift Masks started to be used together with OPC. For the transition from 65nm to 45nm nodes customers were worrying that not only that design rules were insufficient to guarantee printing without yield limiting hotspots, but also that tape-out time may need thousands of CPUs or weeks of run time. This predicted exponential increase in computational complexity for mask synthesis on moving to the 45nm process node spawned a significant venture capital investment in Design for Manufacturing
Design for manufacturability (IC)
Achieving high-yielding designs in the state of the art, VLSI technology has become an extremely challenging task due to the miniaturization as well as the complexity of leading-edge products...
start-up companies. A number of startup companies promoting their own disruptive solutions to this problem, started to appear, techniques from custom hardware acceleration to radical new algorithms such as Inverse Lithography were touted to resolve the forthcoming bottlenecks. Despite all this activity, incumbent OPC suppliers were able to adapt and keep their major customers, with RET and OPC being used together as for previous nodes, but now on more layers and with larger data files, and turn around time concerns were met by new algorithms and improvements in multi-core commodity processors. The term computational lithography was first used by Brion Technology (now a subsidiary of ASML
ASML Holding
ASML is a Dutch company and the largest supplier in the world of photolithography systems for the semiconductor industry. The company manufactures machines for the production of integrated circuits , such as RAM and flash memory chips and CPUs.-Products:...
) in 2005 to promote their hardware accelerated full chip lithography simulation platform. Since then the term has been used by the industry to describe full chip mask synthesis solutions. As 45 nm goes into full production and EUV lithography introduction is delayed, 32 nm and 22 nm are expected to run on existing 193 nm scanners technology. Now, not only are throughput and capabilities concerns resurfacing, but also new computational lithography techniques such as Source Mask Optimization (SMO) is seen as a way to squeeze better resolution specific to a given design. Today, all the major Mask Synthesis vendors have settled on the term "Computational Lithography" to describe and promote the set of Mask Synthesis technologies required for 22 nm.
Techniques comprising computational lithography
Computational lithography makes use of a number of numerical simulations to improve the performance (resolution and contrast) of cutting-edge photomasks. The combined techniques include Resolution Enhancement TechnologyResolution enhancement technologies
Resolution enhancement technologies are methods used to modify photomasks for integrated circuits to compensate for limitations in the lithographic processes used to manufacture the chips....
(RET), Optical Proximity Correction
Optical proximity correction
Optical proximity correction is a photolithography enhancement technique commonly used to compensate for image errors due to diffraction or process effects...
(OPC), Source Mask Optimization (SMO), etc. The techniques vary in terms of their technical feasibility and engineering sensible-ness, resulting in the adoption of some and the continual R&D of others.
Resolution Enhancement Technology (RET)
Resolution Enhancement TechnologyResolution enhancement technologies
Resolution enhancement technologies are methods used to modify photomasks for integrated circuits to compensate for limitations in the lithographic processes used to manufacture the chips....
, first used in the 90 nanometer
90 nanometer
The 90 nm process refers to the level of CMOS process technology that was reached in the 2002–2003 timeframe, by most leading semiconductor companies, like Intel, AMD, Infineon, Texas Instruments, IBM, and TSMC....
generation, using the mathematics of diffraction optics to specify multi-layer phase-shift photomasks that use interference patterns in the photomask that enhance resolution on the printed wafer surface.
Optical Proximity Correction (OPC)
Optical proximity correctionOptical proximity correction
Optical proximity correction is a photolithography enhancement technique commonly used to compensate for image errors due to diffraction or process effects...
uses computational methods to counteract the effects of diffraction-related blurring and under-exposure by modifying on-mask geometries with means such as:
- adjusting linewidths depending on the density of surrounding geometries (a trace surrounded by a large open area will be over-exposed compared with the same trace surrounded by a dense pattern)
- adding "dog-bone" endcaps to the end of lines to prevent line shortening
- correcting for electron beam proximity effectsProximity effect (electron beam lithography)The proximity effect in electron beam lithography is the phenomenon that the exposure dose distribution, and hence the developed pattern, is wider than the scanned pattern, due to the interactions of the primary beam electrons with the resist and substrate...
OPC can be broadly divided into rule-based and model-based.
Inverse lithography technology, which treats the OPC as an inverse imaging problem, is also a useful technique because it can provide unintuitive mask patterns.
Complex modeling of the lens system and photoresist
Beyond the models used for RET and OPC, computational lithographics attempts to improve chip manufacturability and yields such as by using the signature of the scanner to help improve accuracy of the OPC model:- polarization characteristics on of the lens pupil
- Jones matrixJones calculusIn optics, polarized light can be described using the Jones calculus, invented by R. C. Jones in 1941. Polarized light is represented by a Jones vector, and linear optical elements are represented by Jones matrices...
of the stepper lens - optical parameters of the photoresistPhotoresistA photoresist is a light-sensitive material used in several industrial processes, such as photolithography and photoengraving to form a patterned coating on a surface.-Tone:Photoresists are classified into two groups: positive resists and negative resists....
stack - diffusion through the photoresist
- stepper illumination control variables
A CPU-century worth of calculations or more
The computational effort behind these methods is immense. According to one estimate, the calculations required to adjust OPC geometries to take into account variations to focus and exposure for a state-of-the-art integrated circuit will take approximately 100 CPU-years of computer time. This does not include modeling the 3D polarization of the light source or any of the several other systems that will to be modeled in production computational photolithographic mask making flows. Brion Technologies, a subsidiary of ASMLASML Holding
ASML is a Dutch company and the largest supplier in the world of photolithography systems for the semiconductor industry. The company manufactures machines for the production of integrated circuits , such as RAM and flash memory chips and CPUs.-Products:...
, the largest manufacturer of photolithography systems, markets a rack-mounted hardware accelerator dedicated for use in making computational lithographic calculations — a mask-making shop can purchase a large number of their systems to run in parallel. Others have claimed significant acceleration using off-the-shelf graphics cards used for computer gaming.